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source.
This signal is applied to the integrator
circuit
where
the
pulse
trains
are
averaged
to
obtain the demodulation signal.
Since beating down the IF frequency in the first
stage results in an improved
S/N, the effects of
pulse variations are reduced and a higher degree of
modulation
(deviation frequency/carrier
frequen-
cy) is possible,
resulting in better detection
ef-
ficiency.
Multiplex Decoder
This
section
consists
of IC (PA4006-A),
and
contains the PLL system switching signal generator
circuit,
chopper type MPX
decoder, pilot signal
automatic
canceller,
stereo
auto
selector,
VCO
killer
circuit,
muting
amplifier, muting
control
circuit,
and
stereo
reception
indicator
circuit.
The chopper type switching circuit either does
or does not establish a signal, thereby generating
no noise or distortion.
4.3 AM TUNER
The AM tuner section uses three varicap diodes
with an AM tuner IC (HA1138).
The selectable
WIDE
IF
band
for
better
sound
quality
and
NARROW
IF band
feature
for good selectivity
is also included in the AM band.
During NARROW
band operation, an additional ceramic filter is in-
serted into the circuit.
Also during the NARROW
band
mode,
a
high-pass
filter
functioning
to
eliminate
the low
frequency
beat
and
improve
audible
frequency
band balance is inserted into
the detection output circuit.
'Additionally, an AGC
circuit built into the IC
suppresses
performance
degradation
in the pre-
sence of a strong magnetic field.
The bar-antenna
also
features
a
cancellation
coil;
cancellation
current to the coil being supplied by a high-power-
ed AGC circuit.
The cancellation current is con-
trolled by output applied to FET (Q20) from the
RF amp (no. 6 pin).
Muting
control
and SIGNAL
indicator control
is by signals from
Q24 — Q26, the IF amp and
detection
circuit
used
exclusively
for
control
applications.
TO
TUNING
VARI - CAPS
TO MIXER
LOCAL
OSCILLATOR
1
VOLTAGE
ry CONTROLLED
OSCILLATOR
PROGRAMMABLE
COUNTER (1/N)
REFERENCE
=.
OSCILLATOR
©
LOOP
FILTER
PHASE
COMPARATOR
Fig. 4-1
Basic composition of the PLL synthesizer circuit
6
4.4 SYNTHESIZER CIRCUIT
Basic Principle
As may
be noted in Fig. 4-1, the quartz PLL
synthesizer consists of a voltage controlled oscillat-
or (VCO), programmable counter, phase comparat-
or, reference oscillator, and loop filter. With VCO
frequency
represented
as fs, reference frequency
as fr, and the programmable counter division ratio
as N (an integer), loop value is determined by the
equation
fr = fs/N.
In other words, when
fr is
a set value, VCO
frequency (fs) depends on the
division
ratio
(N) of the programmable
counter
and becomes a multiple of fr.
F-9 Synthesizer Circuit
The synthesizer circuit used in the F-9 consists
of the circuit itself, and a control circuit using a
one-chip C-MOS IC (TC9137P).
Generally, due to
limitations in the operating speed of the C-MOS IC,
VCO
output is divided by a ratio of 8 by a high-
speed prescaler such as an ECL
(emitter-coupled-
logic) IC for FM
reception,
then input into the
synthesizer IC.
In this case, the equation becomes
fr = fs/8N, and during 100kHz step operations, fr
becomes
12.5kHz.
Any portion of the 12.5kHz
signal not eliminated by the loop filter leaks into
the local oscillator (VCO)
as signal line residual
noise. TC9137P is used with prescaler IC (TD6104P)
in a dual programmable
counter configuration to
provided
split ratio prescaling according
to the
pulse swallow count method to put the reference
frequency
at 25kHz,
outside
the audible range.
Thus, noise escaping the loop filter is diminished,
and a high S/N is obtained.
®
Reference Signal
The 7.2MHz
crystal oscillator signal at pin
2
and 3 of TC9137P is divided by 288 during FM
reception (25kHz), and by 720 during AM recept-
ion (10kHz),
then input into the phase comparat-
or.
@
Programmable Counter
During FM reception, this signal is output from
pin 38 to control prescaler IC (TD6104P) using
the swallow count method.
During AM reception,
the frequency is split directly.
@
Phase Comparator
The
phase
comparator
compares
the phase of
the output of the programmable counter with that
of the reference signal, and if the phase of pro-
grammable
counter
output signal is found to be
lagging, it lowers the level at pins 34 and 33 by
an amount equivalent to the period of phase lag.
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