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Section VIII
Model
339A
Figure
8-9.
Simplified
Meter
Circuit
Schematic.
input amplifier
A2L4
to
provide
a
1
V rms
(full-scale)
input
signal to the
R
MS
detector
A2U5. The
dc output
of
the
RV1S
detector
is
applied
to
the
input of
the relative
adjust amplifier
A2UI2
which,
in
all
function except
RELative
LEVEL,
acts as a
XI
buffer amplifier.
In
the
RELative
LEVEL
function, the
feed-back path
of
A2U
1
is
completed
by switch
A5S9C
to
allow
the
gain of
A2U
I
to
be
varied.
This permits
the user
to
set
a
reference
level
on
the meter.
The
output
of the
relative
adjust amplifier
is
applied
to a
voltage-to-current
converter
(A2U6.
A2QI.
and
A2Q2)
to
drive
meter
VI
I.
Full-scale
output
current
is
I
mA.
8-43. Oscillator Circuit.
8-44.
Frequency
Generation.
Figure 8-10
shows
a
simplified
schematic
diagram
of the
oscillator circuitry
used
in
the
Model
339A.
The
operating frequency
of the
circuit
is
determined by
a
"bridged
T"
filter
network
in
the
negative feed-back
path
of amplifier
A
1
U
1
.
At
resonant frequency,
the
filter
network
is
at
maximum
impedance and
the negative
feed-back
to
amplifier
A
1
U
is
minimum. The
frequency range
of the
oscillator circuit
is
determined by
the selection of
capacitors
Ca
and
Cb
while
the particular
operating frequency
is
controlled
by
the selection of
resistors R.
8-45.
Amplitude
Control.
The
basic oscillator
output
level
is
determined by
positive
feed-back
resistors Rfl
and
Rf2
and
is
regulated
by
the
amplitude
control
circuitry
shown
in
Figure
8-11.
The
purpose of
the
amplitude
control
circuitry
is
to
monitor
the
oscillator
output
level
and
derive
an
error
signal
to
control
the
gain
of
amplifier
A
1
U
1
.
The
oscillator
output
is
sampled
during
the positive
peaks by
the
peak
detector
circuit
which
stores
a
charge equal
to
the
peak amplitude
of
the out-
put
signal
on
capacitor Ch.
The
charge
on Ch
is
com-
pared
to a
reference voltage
by
difference amplifier
A1U2A.
The
output of
A1U2A
represents the
instan-
taneous amplitude
error
of
the
oscillator signal.
This
signal
is
applied
to integrator
A1U2B
and
through
the
fast
response bypass
circuit
to
summing
amplifier
A1U2C.
The
output
of
the
integrator
(A1U2B)
represents the
average
or
long-term amplitude
error
while the
signal
from
the
fast
response bypass
circuit
represents the
amplitude
error
on
a
cycle-to-cycle
basis.
These two
signals
are
added by
summing
amplifier
A1U2C.
The
resulting
output of
A1U2C
drives control
FET A1Q2
which
acts as
a variable
resistor
in
parallel
with
feed-back
resistor
Rf2
to
adjust
the
gain
of
oscillator
amplifier
A1U1.
8-8
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