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Vitrek V15X-AA11 Installation And Setup

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Model V15X-AA11

Installation and Setup

The Model V15X-AA11 is shipped in an anti-static bag with a styrofoam packing container.
Carefully remove the module from its anti-static bag and prepare to set the various options to
conform to the operating environment. Make sure that all anti-static precautions are taken to
avoid damaging the module.
For an initial test the V15X-AA11 and the VME Single Board Computer (SBC) may be plugged
together without any modification needed.
The following chart shows the strap/switch selections along with their default configurations.
If any of the user requirements vary from the default configuration, consult the following
sections for changing the parameter. Please refer to Appendix A of this manual for the location
of the straps and switches on the V15X-AA11.
Selectable Parameter
Default Value
Slot0/Non-Slot0 Configuration
Slot 0 Configuration
Logical Address
0
System Controller
Enabled

Slot0 Configuration

The V15X-AA11 may be configured as a Slot0 controller or as a non-Slot0 controller. The
V15X-AA11 is shipped from the factory as a Slot0 controller. Several strap and switch setting
must be set to enable the V15X-AA11 Slot0 functionality.
Refer to the SBC manual for
enabling the System Controller.
The V15X-AA11 must first be setup as system controller to assume the responsibilities of a
Slot0 controller. A switch setting on the V15X-AA11 must be set. The switch on the V15X-
AA11 is labeled SW2 and the switch location of interest is position 1. This switch must be
placed in the OPEN (1) position to allow the V15X-AA11 to function as a Slot0 controller. This
switch controls the direction of the VXIbus signals SYSCLK and BCLR. If the V15X-AA11
adapter is configured as a system controller, the must also be configured the same way.
The next selection to be made concerns the VXIbus MODID (Module ID) signal and an internal
signal on the V15X-AA11 indicating Slot0 operation. These selections are made via three of the
switch positions of switch SW2. Position 2 controls the internal indication for Slot0 operation.
This switch must be set to the OPEN (1) position for Slot0 operation. Position 3 of switch SW2
controls the MODID signal 825 ohm pulldown resistor. When the V15X-AA11 is in a Slot0
position, this switch must be set to the OPEN (1) position to disconnect the resistor from the
MODID signal since this resistor is provided on the VXI chassis backplane for the Slot0
position.
1

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Summary of Contents for Vitrek V15X-AA11

  • Page 1: Installation And Setup

    AA11 is labeled SW2 and the switch location of interest is position 1. This switch must be placed in the OPEN (1) position to allow the V15X-AA11 to function as a Slot0 controller. This switch controls the direction of the VXIbus signals SYSCLK and BCLR. If the V15X-AA11 adapter is configured as a system controller, the must also be configured the same way.

  • Page 2: Non-Slot0 Configuration

    ECL driver drives this signal onto the VXIbus. A set of straps on the V15X-AA11 adapter controls whether this signal is sourced onto VXI by the internal clock of the V15X-AA11 or not sourced by the V15X-AA11. To alter the selection, two straps must be moved. The V15X-AA11 is configured at the factory to source the CLK10 signal from the internal clock.

  • Page 3: Logical Address

    When the V15X-AA11 is the Slot0 controller, it must be located in the left-most slot (Slot0) and be set for Logical Address 0. If the V15X-AA11 is not the Slot0 controller, it may be located in any other slot in the chassis and set for Logical Address 1 through 255. To statically assign a Logical Address to the V15X-AA11, simply set the 8-position DIP switch to the desired Logical Address in the range of 1 through 254.

  • Page 4: Clk10 Signal Generation

    CLK10. When the straps are installed in the INT (INTERNAL) position, the CLK10 signals are driven by a clock source on the V15X-AA11. If the V15X-AA11 is to be located in a non- Slot0 position in the chassis, the CLK10 signals must be disabled from driving CLK10 by placing the 2 sets of straps into the NC (NO CONNECTION) position.

  • Page 5: Vxibus Configuration Registers And Operational Registers

    VXI module in the chassis makes the required configuration occur. VXIbus Configuration Registers and Operational Registers The following table shows the various registers located in A16 space for the V15X-AA11 Slot 0 Controller. A16 Offset...

  • Page 6: Device Type Register

    The Device Type Register is a read-only register located at an offset of 02 from the A16 Logical Base Address of the V15X-AA11. This register contains the Model Code of the V15X- AA11. Since the V15X-AA11 is an A16-only device, the entire 16-bits of this field is used for the Model Code.

  • Page 7: Status/Control Register

    . Model Codes for non- Slot0 devices must be in the range of 100 to FFFF . When the V15X-AA11 is configured for non-Slot0 operation, the Model Code returned in this register is 152 . When the V15X-AA11 is configured for Slot0 operation, the 100...
  • Page 8 The Protocol Register is a read-only register located at an offset of 08 from the A16 Logical Base Address of the V15X-AA11. The Protocol Register is accessed by executing a read to this address location and the Signal Register is accessed by writing to this location. The Protocol Register is used to define the communication capabilities of the Message Based Device.

  • Page 9: Write Signal Register

    These bits are not used by the V15X-AA11 and returned as ones. Write Signal Register The Write Signal Register is a write-only register located at an offset of 08 from the A16 Logical Base Address of the V15X-AA11. A write operation to this register address accesses the...
  • Page 10 The Response Register is a read-only register located at an offset of 0A from the A16 Logical Base Address of the V15X-AA11. This register is used to return the status of a device’s communication registers and their associated functions. The following diagram shows the bit layout for the Response Register on the V15X-AA11.

  • Page 11: Suffix High Register

    The Suffix High Register is a read-only register located at an offset of 20 from the A16 Logical Base Address of the V15X-AA11. This register is used in combination with the Suffix Low Register to determine the module model number suffix. The Suffix High Register contains the first two ASCII characters of the suffix and the Suffix Low Register contains the last two characters.

  • Page 12: Suffix Low Register

    The Module Suffix Low Register is a read-only register located at an offset of 22 from the A16 Logical Base Address of the V15X-AA11. This register is used in combination with the Suffix High Register to determine the module model number suffix. The Suffix Low Register contains the last two ASCII characters of the suffix and the Suffix High Register contains the first two characters.

  • Page 13: Interrupt Status Register

    Module ID Register. Before any of the MODID lines can be asserted by the V15X-AA11, the Output Enable bit (bit 13) of this register must be set to a one. When the outputs are enabled, setting a MODID bit location to a one asserts the corresponding MODID signal.

  • Page 14: Interrupt Control Register

    The upper 8-bits reflects the cause of the interrupt. Of the upper 8- bits, only 2 of them are used by the V15X-AA11. Once an interrupt acknowledges cycle occurs, the interrupt source bits that were set in this register when the interrupt vector was read are reset to zero.

  • Page 15: Trigger Interrupt Mask/Trigger Interrupt Source Register

    INTERRUPT REQUEST ENABLE is a write/read bit used to enable/disable the V15X-AA11 from generating an interrupt request to the VMEbus. Setting this bit to a one disables the V15X-AA11 from generating an interrupt request and a zero enables the interrupt request. Not Used This bit is not used and read as a one.
  • Page 16 The Trigger Interrupt Mask/Trigger Interrupt Source Register is located at an offset of 2E from the A16 Logical Base Address of the V15X-AA11. This register serves two purposes, depending on the direction of the transfer. A write operation to this register address accesses the Trigger Interrupt Mask Register.

  • Page 17: Trigger Interrupt Source Clear Register

    The Trigger Source Register is a write-only register located at an offset of 32 from the A16 Logical Base Address of the V15X-AA11. This register is used to source the VXI ECL, VXI TTL. This register allows the trigger signals to be either asserted, negated or pulsed. The...

  • Page 18: Trigger Timer Configuration Register

    The Trigger Timer Configuration Register is a write-only register located at an offset of 34 from the A16 Logical Base Address of the V15X-AA11. This register is used to configure the timer interval and specify the trigger signals to assert once the Trigger Timer expires. The...
  • Page 19 Model V15X-AA11 signals. At a predetermined interval, the enabled trigger signals are pulsed for a period of approximately 1.5 microseconds. The actual register accessed through this A16 address offset is determined by the four most significant bits of the Miscellaneous Control Register at offset 3C .

  • Page 20: Sbc Slave Mode Enable Register

    Model V15X-AA11 The following diagram shows the bit pattern for the Trigger Timer Low Register. Write-Only Bit(s) Mnemonic Meaning 15:0 TMR15:0 TIMER DATA 15 through 0 are write-only bits used to establish the interval at which trigger signals are asserted. This register is used in combination with the Trigger Timer High Register to determine the number of 100 nanoseconds increments between trigger assertion.

  • Page 21: Location Monitor Interrupt Control Register

    The SBC (Single Board Computer) Slave Mode Enable Register is a write-only register located at an offset of 38 from the A16 Logical Base Address of the V15X-AA11. This register is used to enable accesses to the SBC slave mode functions.
  • Page 22 Model V15X-AA11 WDAT RDAT WSGL Read/Write DATA DATA SGNL Bit(s) Mnemonic Meaning 15:8 Not Used These bits are not used and read as zeros. ERROR INTERRUPT SOURCE is a write/read bit which is used to read and to clear the interrupt source generated from an ERROR interrupt.

  • Page 23: Interrupt Status Id Register

    The Miscellaneous Control Register is a write-only register located at an offset of 3C from the A16 Logical Base Address of the V15X-AA11. This register is used to set and clear the ERR bit in the Response Register of the V15X-AA11, to set the WRITE READY and READ READY bits in the Response Register, and to control which buried register is accessed through the Trigger Timer Configuration Register address.

  • Page 24: Read Signal Register

    The Read Signal Register is a read-only register located at an offset of 3C from the A16 Logical Base Address of the V15X-AA11. A write operation to the Signal Register is addressed to offset 08 . This register is used for device to device signaling for message based devices. A...

  • Page 25: Version Number Register

    Logical Base Address of the V15X-AA11. This register is read to determine the revision number of the V15X-AA11’s firmware and hardware. The initial revision of the V15X-AA11 has a firmware revision level of 1.0 and a hardware version of 1.0. The following two diagrams show the various fields of the Version Number Register along with a bit pattern for the initial version.

  • Page 26: Vxi Transfers

    - 17FFFFFF VME Extended Address - 0800 0000 FFFFFFF The complete A16 and A24 addressing range are supported by the V15X-AA11. The A32 addressing range is limited due to the amount of memory that the SBC contains. The following section of sample code shows one method of accessing a VXI address. This function is used for returning a 32-bit data value from a VXI module in A32 address space.

  • Page 27: Vxi Triggers

    0, wait for a period of time, negate ECL trigger 0, wait for a period of time, and then negate VXI trigger line 5. The V15X-AA11 is set for Logical Address 0, which results in a A16 Logical Base Address of C000 Shown in pseudocode, the trigger sequence can be sourced as follows: short_a16_write ( 0xC032, 0x120);...
  • Page 28 , and the Trigger Timer Control is loaded with 8010 . The V15X-AA11 is set for Logical Address 0, which results in a A16 Logical Base Address of C000 Shown in pseudocode, the trigger sequence can be setup as follows: short_a16_write ( 0xC03C, 0x00);...
  • Page 29 The trigger sources include the eight VXI TTL trigger lines, two VXI ECL trigger lines. Each bit set to a one enables the trigger source to be latched by the V15X-AA11. Once an enabled trigger source has been latched by the V15X-AA11, it may be read through the...
  • Page 30 Model V15X-AA11 short_a16_write ( 0xC02E, 0x01); /* 16-bit A16 write to address 0xc02e with data of 0x01 */ /* load interrupt mask register to enable VXI TTL trigger 0 */ data = 0; /* set a data variable to zero */...
  • Page 31 Model V15X-AA11 APPENDIX A...
  • Page 32 Model V15X-AA11 APPENDIX B This Appendix shows the allocation of signals on the VXIbus P1 and P2 Connectors. VXI P1 Connector Assignments: Row A Row B Row C BBSY* No Connect No Connect BG0IN* BG0OUT* BG1IN* BG1OUT* BG2IN* BG2OUT* SYSCLK...
  • Page 33 Model V15X-AA11 VXI P2 Connector Assignments: Row A Row B Row C ECLTRG0 +5 V CLK10+ -2 V CLK10- ECLTRG1 RESERVED -5.2 V MODID12 LBUSC00 MODID11 LBUSC01 -5.2 V MODID10 LBUSC02 MODID09 LBUSC03 MODID08 LBUSC04 MODID07 LBUSC05 -5.2 V +5 V...

  • Page 34: Table Of Contents

    CONTENTS INSTALLATION AND SETUP ........................1 SLOT0 CONFIGURATION ..........................1 NON-SLOT0 CONFIGURATION........................2 LOGICAL ADDRESS ............................3 CLK10 SIGNAL GENERATION ........................4 INSTALLATION ............................... 4 VXIBUS CONFIGURATION REGISTERS AND OPERATIONAL REGISTERS ......... 5 ID/LOGICAL ADDRESS REGISTER ......................5 DEVICE TYPE REGISTER ..........................6 STATUS/CONTROL REGISTER ........................
  • Page 35 Model V15X-AA11 READ SIGNAL REGISTER .......................... 24 VERSION NUMBER REGISTER ........................ 25 VXI TRANSFERS ............................26 VXI TRIGGERS............................... 27 SYNCHRONOUS TRIGGER EXAMPLE....................27 START/STOP TRIGGER EXAMPLE ......................27 APPENDIX A..............................31 APPENDIX B..............................32...

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