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PIN
TYPE
NAME
NO.
DVSS
28
GND
29
GVDD_OUT
5, 32
LRCLK
20
MCLK
15
OC_ADJ
7
AO
OSC_RES
16
AO
OUT_A
1
OUT_B
46
OUT_C
39
OUT_D
36
PBTL
8
PDN
19
PGND_AB
47, 48
PGND_CD
37, 38
PLL_FLTM
10
AO
PLL_FLTP
11
AO
PVDD_A
2, 3
PVDD_B
44, 45
PVDD_C
40, 41
PVDD_D
34, 35
RESET
25
SCL
24
SCLK
21
SDA
23
DIO
SDIN
22
SSTIMER
6
STEST
26
VR_ANA
12
VR_DIG
18
VREG
31
PIN FUNCTIONS (continued)
5-V
(1)
TERMINATION
TOLERANT
P
P
P
DI
5-V
Pulldown
DI
5-V
Pulldown
O
O
O
O
DI
DI
5-V
P
P
P
P
P
P
DI
5-V
DI
5-V
DI
5-V
Pulldown
5-V
DI
5-V
Pulldown
AI
DI
P
P
P
(2)
Digital ground
Analog ground for power stage
Gate drive internal regulator output. This pin must not be used to
drive external devices.
Input serial audio data left/right clock (sample rate clock)
Master clock input
Analog overcurrent programming. Requires resistor to ground.
Oscillator trim resistor. Connect an 18.2-kΩ 1% resistor to DVSSO.
Output, half-bridge A
Output, half-bridge B
Output, half-bridge C
Output, half-bridge D
Low means BTL or SE mode; high means PBTL mode. Information
goes directly to power stage.
Pullup
Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the Noise Shaper and initiating PWM stop
sequence.
Power ground for half-bridges A and B
Power ground for half-bridges C and D
PLL negative loop filter terminal
PLL positive loop filter terminal
Power supply input for half-bridge output A
Power supply input for half-bridge output B
Power supply input for half-bridge output C
Power supply input for half-bridge output D
Pullup
Reset, active-low. A system reset is generated by applying a logic
low to this pin. RESET is an asynchronous control signal that
restores the DAP to its default conditions, and places the PWM in
the hard mute state (tristated).
2
I
C serial control clock input
Serial audio data clock (shift clock). SCLK is the serial audio port
input data bit clock.
2
I
C serial control data interface input/output
Serial audio data input. SDIN supports three discrete (stereo) data
formats.
Controls ramp time of OUT_x to minimize pop. Leave this pin
floating for BD mode. Requires capacitor of 2.2 nF to GND in AD
mode. The capacitor determines the ramp time.
Factory test pin. Connect directly to DVSS.
Internally regulated 1.8-V analog supply voltage. This pin must not
be used to power external devices.
Internally regulated 1.8-V digital supply voltage. This pin must not be
used to power external devices.
Digital regulator output. Not to be used for powering external
circuitry.
DESCRIPTION
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