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Summary of Contents for Supermicro SUPER P6DGE
- Page 1 ® UPER SUPER P6DGS SUPER P6DGE SUPER P6DGU SUPER P6SGU USER’S MANUAL Revision 2.2...
- Page 2 SUPERMICRO COMPUTER reserves the right to make changes to the product described in this manual at any time and without notice. This product, including software, if any, and documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or reduced to any medium or machine without prior written consent.
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Page 3: About This Manual
66MHz bus speed and Pentium II/III 350-700 MHz processors at a 100MHz bus speed and Slot 1 Celeron processors of up to 466 MHz. The SUPER P6DGU/P6DGS/P6DGE supports single or dual Pentium II/III proces- sors and the SUPER P6SGU supports a single Pentium II/III processor. - Page 4 User’s Manual SUPER P6DGS/P6DGE/P6DGU/P6SGU asked questions] section is provided. Instructions are also included for tech- nical support procedure, for returning merchandise for service and for BIOS upgrades. See Chapter 4 for configuration data and BIOS features. Chapter 5 has information on running setup and includes the default settings for Standard Setup, Advanced Setup, Chipset function, Power Management, PCI/PnP Setup and Peripheral Setup.
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Page 5: Table Of Contents
Overview ... 1-1 SUPER P6DGS ... 1-2 SUPER P6DGS Motherboard Layout ... 1-3 SUPER P6DGE ... 1-4 SUPER P6DGE Motherboard Layout ... 1-5 SUPER P6DGU ... 1-6 SUPER P6DGU Motherboard Layout ... 1-7 SUPER P6SGU ... 1-8 SUPER P6SGU Motherboard Layout ... 1-9 440GX AGP Chipset: System Block Diagram ... - Page 6 SUPER P6DGS/P6DGE/P6DGU/P6SGU Power Supply Connector ... 2-7 Secondary Power Connector ... 2-7 Infrared Connector ... 2-7 PW_ON Connector ... 2-8 Reset Connector ... 2-8 Hard Drive LED ... 2-8 Keylock/Power LED Connector ... 2-8 Speaker Connector ... 2-9 Power Save State Select ... 2-9 ATX PS/2 Keyboard and Mouse Ports ...
- Page 7 Chapter 4: AMIBIOS Introduction ... 4-1 BIOS Features ... 4-2 BIOS Configuration Summary Screen ... 4-3 AMIBIOS Setup ... 4-3 Chapter 5: Running Setup Setup ... 5-1 5-1-1 Standard Setup ... 5-1 5-1-2 Advanced Setup ... 5-3 5-1-3 Chipset Setup ... 5-7 5-1-4 Power Management ...
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Page 8: Jumper/Connector Quick Reference
SUPER P6DGS/P6DGE/P6DGU/P6SGU Jumper/Connector Quick Reference P 6 D G S / P 6 D G E Jumper Function JB1, JB2, JB3, JB4 CPU/Bus Ratio Selection J B T 1 CMOS Clear J P 2 0 Power Save State Select Manufacturer Default... -
Page 9: Front Control Panel Connector
Front Control Panel Connector Please see pages 2-7 through 2-9 for pin definitions. JF2 JF1 H a r d Drive L E D IR Con P o w e r L E D K e y b o a r d lock P o w e r O n S p e a k e r... - Page 10 Preface Notes...
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Page 11: Chapter 1: Introduction
While all of the motherboards are the ATX form factor, the P6DGU and P6DGE have 5 PCI and 2 ISA slots with one slot shared. The SUPER P6DGS and P6SGU have 4 PCI and 3 ISA slots with one slot shared. -
Page 12: Super P6Dgs
Manual SUPER P6DGS/P6DGE/P6DGU/P6SGU SUPER P6DGS Figure 1-1. SUPER P6DGS/P6DBS Motherboard Picture (Both boards share the same PCB) -
Page 13: Super P6Dgs Motherboard Layout
PS/2 KB (bottom) PS/2 MOUSE (top) J17, J18 U S B J 1 9 P a r a l l e l Port JP20 PCI 4 PCI 3 C h a s s i s Intrusion J T M PCI 2 PCI 1 JJ14 I S A... -
Page 14: Super P6Dge
Manual SUPER P6DGS/P6DGE/P6DGU/P6SGU SUPER P6DGE Figure 1-3. SUPER P6DGE/P6DBE Motherboard Picture (Both boards share the same PCB) -
Page 15: Super P6Dge Motherboard Layout
1-2 PIIX CTL PD State 2-3 BIOS CTL PD State (default) WOL: Wake-on-LAN ——–—–——————–———–——–——–— *Note: To Enable the Overheat Buzzer place a jumper on BZ_On. Figure 1-4. SUPER P6DGE Motherboard Layout 9.6" JP16 JP11 P I I X 4 JP18 9.6"... -
Page 16: Super P6Dgu
Manual SUPER P6DGS/P6DGE/P6DGU/P6SGU SUPER P6DGU Figure 1-5. SUPER P6DGU/P6DBU Motherboard Picture (Both boards share the same PCB) -
Page 17: Super P6Dgu Motherboard Layout
PS/2 KB (bottom) PS/2 MOUSE (top) J 1 7 , J 1 8 U S B J 1 9 P a r a l l e l Port JP20 PCI 5 PCI 4 C h a s s i s Intrusion J T M J L 2... -
Page 18: Super P6Sgu
Manual SUPER P6DGS/P6DGE/P6DGU/P6SGU SUPER P6SGU Figure 1-7. SUPER P6SGU Motherboard Picture (OEM board only) -
Page 19: Super P6Sgu Motherboard Layout
PS/2 KB (bottom) PS/2 MOUSE (top) J 1 7 , J 1 8 U S B JOH1: Overheat LED JA5,JA6: SCSI Termination J 1 9 P a r a l l e l Port L I N E L I N E M I C 12"... -
Page 20: 440Gx Agp Chipset: System Block Diagram
Manual SUPER P6DGS/P6DGE/P6DGU/P6SGU C P U C P U Host Bus S D R A M A G P 440GX Port PCI Slots SMBus APIC PIIX4 IDE Ports Power SCSI Management U S B Ports ISA Slots BIOS Figure 1-9. 440GX AGP Chipset:... - Page 21 Features of the P6DGS, P6DGE, P6DGU and P6SGU The following list covers the general features of the SUPER P6DGS, P6DGE, P6DGU and P6SGU. • Single or dual Pentium II 233/266/300/333 MHz processors at 66 MHz bus speed or Pentium II/III 350/400/450/500/550/600/650/700 MHz processors at 100 MHz bus speed III processor.) Note: Please refer to the support section of our web site for a complete listing...
- Page 22 • SCSI Utility, manual and driver Dimensions • SUPER P6DGS - ATX (12" x 9.65") • SUPER P6DGE - ATX (12" x 9.6") • SUPER P6DGU - ATX (12" x 9.65") • SUPER P6SGU - ATX (12" x 8.875") Manual ®...
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Page 23: Chipset Overview
PC Health Monitoring This section describes the PC health monitoring features of the SUPER P6DGS, P6DGE, P6DGU and P6SGU. All have an onboard System Hardware Monitor chip that supports PC health monitoring. Seven Onboard Voltage Monitors for the CPU Core(s), CPU I/O, +3.3V, ±... - Page 24 JL1. When the micro-switch is closed, it means that the chassis has been opened. message when the system is turned on. This feature is available when the user is running Intel's LANDesk Client Manager, and SUPERMICRO's Super Doctor. System Resource Alert This feature is available when used with Intel's LANDesk Client Manager (optional).
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Page 25: Solo-1 Pci Audio Drive
The system BIOS is protected by hardware so that no virus can infect the BIOS area. The user can only change the BIOS content through the flash utility provided by SUPERMICRO. infecting the BIOS area and destroying valuable data. Auto-Switching Voltage Regulator for the CPU Core The switching voltage regulator for the CPU core can support up to 20A of current, with auto-sensing voltage ID ranging from 1.8V to 3.5V. -
Page 26: Acpi/Pc 98 Features
SUPER P6DGS/P6DGE/P6DGU/P6SGU ACPI/PC 98 Features ACPI stands for Advanced Configuration and Power Interface. specification defines a flexible and abstract hardware interface that pro- vides a standard way to integrate power management features throughout a PC system, including hardware, operating system and application soft- ware. -
Page 27: Power Supply
LAN traffic is kept to a minimum and users are not interrupted. The motherboards have a 3-pin header (WOL) used to connect to the 3-pin header on a Network Interface Card (NIC) that has WOL capability. Note that Wake-on-Lan can only be used with an ATX 2.01 (or above) compliant... -
Page 28: Super I/O
SUPER P6DGS/P6DGE/P6DGU/P6SGU The SUPER P6DGS/P6DGE/P6DGU/P6SGU accommodates ATX power sup- plies. Although most power supplies generally meet the specifications required by the CPU, some power supplies are inadequate. It is highly recommended that you use a high quality power supply that meets ATX power supply specification 2.01. -
Page 29: Aic-7890 Scsi Controller
AIC-7895 MultiChannel The SUPER P6DGS has an onboard SCSI controller that is 100% compatible with all major operating and hardware platforms. PCI 2.1 and SCAM Level 1 compliance are assured. Two independent SCSI channels provide a per channel data transfer rate of 40 MB/s. Connectors include two 68-pin, 16-bit Ultra Wide SCSI connectors (JA1/JA2) and a 50-pin, 8-bit SCSI connector (JA3). - Page 30 Manual SUPER P6DGS/P6DGE/P6DGU/P6SGU controller can support external High Voltage Differential (HVD) transceivers only for Ultra data rates. When installing Windows NT, refer to the relevant question/answer in the FAQ section of this manual. 1-20...
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Page 31: Chapter 2: Installation
Static-Sensitive Devices Static-sensitive electric discharge can damage electronic components. prevent damage to your system board, it is important to handle it very carefully. The following measures are generally sufficient to protect your equipment from static discharge. Precautions • Use a grounded wrist strap designed for static discharge. •... - Page 32 SUPER P6DGS/P6DGE/P6DGU/P6SGU Install the Universal Retention Mechanism (URM) under the mother- board. Do this before mounting the motherboard into the chassis. Do not screw too tightly. Mount the two black plastic pegs onto the motherboard (Figure 2.1). These pegs will be used to attach the fan heatsink supports.
- Page 33 slide into the holes in the heatsink support and that the alignment notch in the SEC cartridge fits over the plug in Slot 1. firmly, with even pressure on both sides of the top, until it is seated. Figure 2-2. Top of Processor Slide the clips on the supports (A) forward until they click into place to hold the pegs securely.
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Page 34: Installation Of The Universal Retention Mechanism
SUPER P6DGS/P6DGE/P6DGU/P6SGU Figure 2-3. Installation of the Universal Retention Mechanism (URM)* Please Note! Screws and washers attach from the bottom of the board and must be installed before mounting the board to the chassis. (See Figures 2-4 and 2-5.) When installing the URM, make sure that the Left (L) and the Right (R) sides are placed accordingly. - Page 35 Chapter 2: Installation Figure 2-4. URM and Celeron Installation Supero Screw holes for retention URM with arms folded mechanism Note: Left and Right arms are defined Note notch in socket Top view of Celeron cap Figure 2-5. Installing a Slot 1 Processor...
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Page 36: Explanation And Diagram Of Jumper/Connector
SUPER P6DGS/P6DGE/P6DGU/P6SGU Explanation and Diagram of Jumper/ Connector To modify the operation of the moth- erboard, jumpers can be used to choose settings. Jumpers create shorts between two pins and change the function of the connector. Pin 1 is identified with a square. -
Page 37: Mounting The Motherboard In The Chassis
Mounting the Motherboard in the Chassis All the motherboards have standard mounting holes to fit different types of chassis. Chassis may come with a variety of mounting fasteners, made of metal or plastic. Although a chassis may have both metal and plastic fas- teners, metal fasteners are the most highly recommended because they ground the system board to the chassis. -
Page 38: Pw_On Connector
SUPER P6DGS/P6DGE/P6DGU/P6SGU PW_ON Connector The PW_ON connector is located on pins 9 and 10 of JF2. Momen- tarily contacting both pins will power on/off the system. user can also configure this but- ton to function as a suspend but- ton. (See BIOS setup information on page 5-13). -
Page 39: Atx Ps/2 Keyboard And Mouse Ports
Speaker Connector The speaker connector is located on pins 10 to 13 of JF1. See Table 2-9 for pin definitions. Power Save State Select Refer to Table 2-10 to set JP20. Power Save State Select is used when you want the system to be in power off state the first time you apply power to the system or when the system comes back... -
Page 40: Atx Serial Ports
SUPER P6DGS/P6DGE/P6DGU/P6SGU ATX Serial Ports ATX serial port COM1 is located on J20 and serial port COM2 is located on J21. See Table 2-13 for pin definitions. CMOS Clear Refer to Table 2-14 for instructions on how to clear the CMOS. For ATX... -
Page 41: Chassis Intrusion
Chassis Intrusion The Chassis Intrusion Detector is located on JL1. See the board lay- outs and the PC Health Monitoring sections in Chapter One for more in- formation. See Table 2-18 for pin definitions. Installing DIMMs Exercise extreme care when installing or removing DIMM modules to prevent any possible damage. -
Page 42: Connecting Parallel, Floppy And Hard Disk Drives
SUPER P6DGS/P6DGE/P6DGU/P6SGU Side View of DIMM Installation into Socket PC100 To Install: Notches Insert vertically, press down until it snaps into place. Pay attention to the two notches. Top View of DIMM Socket Connecting Parallel, Floppy and Hard Disk Drives Use the following information to connect the floppy and hard disk drive cables. -
Page 43: Parallel Port Connector
two hard disk drives and the SCSI adapter. (Note: most SCSI hard drives are single-ended SCSI devices.) The SCSI ID is determined by jumpers or a switch on the SCSI device. The last internal (and external) SCSI device cabled to the SCSI adapter must be terminated. Table 2-19 Parallel Port Pin Definitions (J19) Pin Number... -
Page 44: Scsi Connectors
SUPER P6DGS/P6DGE/P6DGU/P6SGU SCSI Connectors There are no jumpers to configure the onboard Single Ended SCSI in- terface. Refer to Table 2-22 for pin definitions. Refer to Table 2-23 for the pin definitions of the 50-pin SCSI interface. (See board layouts for the names and locations of SCSI con- nectors.) -
Page 45: 68-Pin Lvd Scsi Connector
Table 2-24 68-Pin LVD SCSI Connector Pin Definitions Connector Contact N u m b e r Signal Names +DB(12) +DB(13) +DB(14) +DB(15) +DB(P1) +DB(0) +DB(1) +DB(2) +DB(3) +DB(4) +DB(5) +DB(6) +DB(7) +DB(P) G R O U N D D I F F S E N S T E R M P W R T E R M P W R R E S E R V E D... -
Page 46: Agp Port
SUPER P6DGS/P6DGE/P6DGU/P6SGU Pin # Manual Table 2-25 AGP Port Pin Definitions (J8) Pin # Spare 1 2 V Vddq3.3 5.0V Spare A D 2 1 5.0V Reserved* A D 1 9 U S B + U S B - G N D... -
Page 47: Troubleshooting Flowchart
Troubleshooting Procedures Use the following procedures and chart to troubleshoot your system. If you have followed all of the procedures below and still need assistance, refer to the ‘Tech- nical Support Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter. Before Power On Make sure no short circuits exist between the motherboard and chassis. -
Page 48: No Power
SUPER P6DGS/P6DGE/P6DGU/P6SGU No Power Make sure the default jumper is on and the CPU is correctly set up. Turn the power switch on and off to test the system. If power is still not on, turn off system power to move jumper setting on JP20 from 2-3 to 1-2. -
Page 49: Losing The System's Setup Configuration
Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked Question' (FAQ) sections in this chapter of the manual or check our web site FAQs (http://www.supermicro.com) before contacting Technical Support. Take note that as a motherboard manufacturer, Super Micro does not sell directly to end-users, so it is best to check with your distributor or reseller for troubleshooting services. -
Page 50: Frequently Asked Questions
4. User should populate memory starting with the DIMM socket located the furthest from the GX chip (U2 on P6DGS/P6DGE or U4 on P6DGU/P6SGU). Question: How do I update my BIOS? Answer: It is recommended that you do not update your BIOS if you are experiencing no problems with your system. - Page 51 I have memory problems. to use and which BIOS setting should I choose? Answer: The correct memory to use on the SUPER P6DGS/P6DGE/P6DGU/ P6SGU is 168-pin DIMM 3.3v non-buffered SPD (Serial Present Detection) SDRAM and SDRAM. SPD SDRAM is preferred but is not necessary. IMPOR- TANT: Please do not mix memory types;...
- Page 52 SUPER P6DGS/P6DGE/P6DGU/P6SGU Question: Why can't I turn off the power using the momentary power on/off switch? Answer: The instant power off function is controlled by the BIOS. When this feature is enabled in the BIOS, the motherboard will have instant off capabilities as long as the BIOS has control of the system.
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Page 53: Returning Merchandise For Service
Answer: No jumper or BIOS setting changes are necessary whether running a single or dual processor on the P6DGS/P6DGE/P6DGU board. Also, if running a single processor, it can be installed in either CPU slot, although we recommend using the slot nearest to the chipset (J2). - Page 54 Manual SUPER P6DGS/P6DGE/P6DGU/P6SGU Notes...
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Page 55: Chapter 4: Amibios
Introduction This chapter describes the AMIBIOS for Intel 440GX Pentium II/III 600/550/ 500/450/400/350/333/300/266/233 MHz processors. The AMI ROM BIOS is stored in the Flash EEPROM and is easily upgraded using a floppy disk- based program. System BIOS The BIOS is the Basic Input Output System used in all IBM ®... -
Page 56: Bios Features
BIOS User's Manual American AMIBIOS (c) 1997 American Megatrends, Inc. M e g a Trends 0404981500 Pentium II Motherboard Made in USA R1.0 U P E R BIOS date code Checking NVRAM xxxxx KB OK Hit <DEL> if you want to run SETUP (C) Super Micro Computer, Inc., XX-XXXX-XXXXXX-XXXXXXXX-XXXXXX-XXXX-X BIOS Features... -
Page 57: Bios Configuration Summary Screen
• five positive voltage inputs • two negative voltage inputs • three fan speed monitoring inputs BIOS Configuration Summary Screen AMIBIOS displays a screen that looks similar to the following when the POST routines complete successfully. AMIBIOS System Configuration (C) 1985-1997 American Megatrends Inc., Main Processor : Pentium(tm) II Math Processor... - Page 58 BIOS User's Manual Figure 4-1. Standard Option Highlighted Figure 4-2. Settings for Standard Option...
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Page 59: Chapter 5: Running Setup
*Optimal and Fail-Safe default settings are bolded in text unless otherwise The WinBIOS Setup options described in this section are selected by choosing the appropriate high-level icon from the Standard Setup screen. All displayed icons are described in this section, although the screen display is often all you need to understand how to set the options. - Page 60 BIOS User's Manual not workproperly. If you are absolutely certain that you know the drive's PIO mode, select PIO mode 0-4, as appropriate Select Type . Select CDROM . Click on OK when AMIBIOS displays the drive parameters. Entering Drive Parameters You can also enter the hard disk drive parameters.
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Page 61: Advanced Setup
3½ inch , 1.44 MB 3½ inch or 2.88 MB 3½ inch . Note: The Optimal and Fail-Safe settings for Floppy Drive A are 1.44 MB 3 1/2 inch and for Floppy Drive B are Not Installed . 5-1-2 Advanced Setup Quick Boot The Settings are Disabled or Enabled . - Page 62 BIOS User's Manual 1st Boot Device 2nd Boot Device 3rd Boot Device The options for 1st Boot Device are Disabled, 1st IDE-HDD, 2nd IDE- HDD, 3rd IDE-HDD, 4th IDE-HDD, Floppy, ARMD-FDD, ARMD-HDD, ATAPI CD ROM, SCSI, Network or I 0 . The options for 2nd Boot Device are Disabled, 1st IDE-HDD, 2nd IDE-HDD, 3rd IDE-HDD, 4th IDE-HDD, Floppy, ARMD-FDD, ARMD-HDD or ATAPI CD ROM .
- Page 63 Chapter 5: Running Setup Display Mode at Add-on ROM Init This option determines the display mode during add-on ROM (except Video add-on ROM) initialization. The settings for this option are Force BIOS or Keep Current . If selected as Force BIOS, the POST will force the display to be changed to BIOS mode before giving control to any add- on ROM.
- Page 64 BIOS User's Manual password prompt appears every time the computer is turned on. If Setup is chosen, the password prompt appears if WinBIOS Setup is executed. Boot to OS/2 If DRAM size is over 64 MB, set this option to Yes to permit AMIBIOS to run with IBM OS/2.
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Page 65: Chipset Setup
Chapter 5: Running Setup C800, 16K Shadow CC00, 16K Shadow D000, 16K Shadow D400, 16K Shadow D800, 16K Shadow DC00, 16K Shadow These options enable shadowing of the contents of the ROM area named in the option. The ROM area not used by ISA adapter cards is allocated to PCI adapter cards. - Page 66 BIOS User's Manual outside of main DRAM range (i.e. in the 640k - 1M range or above TOM) - The GX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture. - The GX asserts SERR# for one clock when it detects a target abort during GX initiated AGP cycle PERR# This option signals data parity errors of the PCI bus.
- Page 67 Memory Autosizing Support The dynamic detection and sizing of SDRAM and EDO is performed by the BIOS in a system populated with memory which has no SPD information. When set to Enable , memory does not have the SPD information. The settings for this option are Auto or Enable .
- Page 68 BIOS User's Manual DRAM Refresh Rate This option specifies the interval between Refresh signals to DRAM system memory. The settings for this option are 15.6 us (micro-sec- onds), 31.2 us , 62.4 us , 124.8 us or 249.6 us . Memory Hole This option specifies the location of an area of memory that cannot be addressed on the ISA bus.
- Page 69 Chapter 5: Running Setup Gated Clock Signal GCLKEN enables internal dynamic clock gating in the GX when a AGPset "IDLE" state occurs. This happens when the GX detects an idle state on all its buses. The settings for this option are Enabled or Disabled .
- Page 70 BIOS User's Manual 8bit I/O Recovery Time This option specifies the length of a delay inserted between consecutive 8-bit I/O operations. The settings are Disabled , 1 SYSCLK , 2 SYSCLKs , 3 SYSCLKs , 4 SYSCLKs , 5 SYSCLKs , 6 SYSCLKs , 7 SYSCLKs or 8 SYSCLKs .
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Page 71: Power Management
Chapter 5: Running Setup DMA6 Type DMA7 Type These options specify the bus that the specified DMA channel can be used on. The settings are PC/PCI , Distributed , or Normal ISA . Memory Buffer Strength The settings for this option are Strong or Auto . Manufacturer's Setting Note: The user should always set this option to mode 0. - Page 72 BIOS User's Manual Hard Disk Power Down Mode This option specifies the power conserving state that the hard disk drive enters after the specified period of hard drive inactivity has expired. The settings are Disabled , Standby , or Suspend . Note: The Optimal default setting for this option is Suspend and the Fail-Safe default setting is Disabled .
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Page 73: Pci/Pnp Setup
Chapter 5: Running Setup no display activity for the length of time specified in the Standby Timeout (Minute) option, the computer enters a power savings state. The settings are Monitor or Ignore . Device 6 (Serial port 1) Device 7 (Serial port 2) Device 8 (Parallel port) Device 5 (Floppy disk) Device 0 (Primary Master IDE) - Page 74 BIOS User's Manual PCI VGA Palette Snoop The settings for this option are Disabled or Enabled. When set to Enabled, multiple VGA devices operating on different buses can handle data from the CPU on each set of palette registers on every video device. Bit 5 of the command register in the PCI device configuration space is the VGA Palette Snoop bit (0 is disabled).
- Page 75 Chapter 5: Running Setup PCI Slot1 IRQ Priority PCI Slot2 IRQ Priority PCI Slot3 IRQ Priority PCI Slot4 IRQ Priority These options specify the IRQ priority for PCI devices installed in the PCI expansion slots. The settings are Auto, (IRQ) 3, 4, 5, 7, 9, 10, or 11, in priority order .
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Page 76: Peripheral Setup
The settings for this option are Enabled or Disabled . When set to Enable this option enables the Adaptec 7895 BIOS on the P6DGS/P6SGS motherboards or the Adaptec 7890 on the P6DGU/P6SGU motherboards. Remote Power On Microsoft's Memphis OS supports this feature which can wake-up the system from SoftOff state through devices (such as an external modem) that are connected to COM1 or COM2. - Page 77 CPU2 Fan Thermal Control Fan The above features are for PC Health Monitoring. The motherboards with W83781D have seven on-board voltage monitors for the CPU core, CPU I/ O, +3.3V, +5V, -5V, +12V, and -12V, and three fan status monitors.
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Page 78: Security Setup
BIOS User's Manual Parallel Port Mode This option specifies the parallel port mode. The settings are Normal , Bi- Dir , EPP or ECP . When set to Normal, the normal parallel port mode is used. Use Bi-Dir to support bidirectional transfers. Use EPP (Enhanced Parallel Port) to provide asymmetric bidirectional data transfer driven by the host device. -
Page 79: Utility Setup
The password check option is enabled in the Advanced Setup by choosing either Always or Setup . The password is stored in CMOS RAM. You can enter a password by typing the password on the keyboard, selecting each letter via the mouse, or selecting each letter via the pen stylus. -
Page 80: Fail-Safe Default
BIOS User's Manual 5-4-2 Fail-Safe Default The Fail-Safe default settings consist of the safest set of parameters. Use them if the system is behaving erratically. They should always work but do not provide optimal system performance characteristics. 5-22... -
Page 81: Appendix A: Bios Error Beep Codes
Appendix A: BIOS Error Beep Codes Appendix A BIOS Error Beep Codes & Messages During the POST (Power-On Self-Test) routines, which are performed each time the system is powered on, errors may occur. Non-fatal errors are those which, in most cases, allow the system to continue the boot-up process. - Page 82 BIOS Manual Beeps Error message Refresh Failure Parity Error Base 64 KB Memory Failure Timer Not Operational Processor Error 8042 - Gate A20 Failure Processor Exception Interrupt Error Display Memory Read/Write Error ROM Checksum Error CMOS Shutdown Register Read/Write Error Refer to the table on page A-3 for solutions to the error beep codes.
- Page 83 If it beeps... 1, 2, 3 times 6 times 8 times 9 times 4, 5, 7, or 10 times Appendix A: BIOS Error Beep Codes then ... reseat the DIMM memory. system still beeps, replace the memory. reseat the keyboard controller chip. If it still beeps, replace the keyboard controller.
- Page 84 BIOS Manual Error Message 8042 Gate -- A20 Error Address Line Short! C: Drive Error C: Drive Failure Cache Memory Bad CH-2 Timer Error CMOS Battery State Low CMOS Checksum Failure CMOS System Option Not Set CMOS Display Type Mismatch CMOS Memory Size Mismatch Information...
- Page 85 Error Message CMOS Time and Date Not Set D: Drive Error D: Drive Failure Diskette Boot Failure Display Switch Not Proper DMA Error DMA #1 Error DMA #2 Error FDD Controller Failure HDD Controller Failure INTR #1 Error INTR #2 Error Appendix A: BIOS Error Beep Codes Information Run Standard Setup to set the date and time...
- Page 86 BIOS Manual Error Message Invalid Boot Diskette Keyboard Is Locked... Unlock It Keyboard Error KB/Interface Error No ROM BASIC Off Board Parity Error On Board Parity Error Parity Error???? Information The BIOS can read the disk in floppy drive A:, but cannot boot the computer. Use another boot disk.
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Page 87: Appendix B: Amibios Post Diagnostic Error Messages
Appendix B: AMIBIOS POST Diagnostics Error Messages AMIBIOS POST Diagnostic Error Messages This section describes the power-on self-test's (POST) port 80 codes for the AMIBIOS. Check Point Description Code copying to specific areas is done. to INT 19h boot loader next. NMI is Disabled. - Page 88 BIOS Manual Check Point Description The keyboard controller command byte is written. Next, issuing the pin 23 and 24 blocking and unblocking commands. Next, checking if the <End or <Ins> keys were pressed during Initialize CMOS RAM in every boot AMIBIOS POST option was set in AMIBCP or the <End>...
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Page 89: Appendix B: Amibios Post Diagnostics Error Messages
Appendix B: AMIBIOS POST Diagnostics Error Messages Check Point Description Initialization before setting the video mode is complete. Configuring the monochrome mode and color mode settings next. Bus initialization system, static, output devices will be done next, if present. Passing control to the video ROM to perform any required configuration before the video ROM test. - Page 90 BIOS Manual Check Point Description Initializing the bus input, IPL, and general devices next, if present. Displaying bus initialization error messages. The new cursor position has been read and saved. Displaying the Hit <DEL> message next. Preparing the descriptor tables next. The descriptor tables are prepared.
- Page 91 Appendix B: AMIBIOS POST Diagnostics Error Messages Check Point Description The memory below 1 MB has been cleared via a soft reset. Clearing the memory above 1 MB next. The memory above 1 MB has been cleared via a soft reset.
- Page 92 BIOS Manual Check Point Description The DMA page register test passed. DMA Controller 1 base register test next. The DMA controller 1 base register test passed. Performing the DMA controller 2 base register test next. The DMA controller 2 base register test passed. Programming DMA controllers 1 and 2 next.
- Page 93 Appendix B: AMIBIOS POST Diagnostics Error Messages Check Point Description programming been completed. Uncompressing the WINBIOS Setup code and executing the AMIBIOS Setup or WINBIOS Setup utility next. Returned from WINBIOS Setup and cleared the screen. Performing any necessary programming after WINBIOS Setup next.
- Page 94 BIOS Manual Check Point Description Any initialization required after the option ROM test has been completed. printer base address next. Set the timer and printer base addresses. RS-232 base address next. Returned Performing Coprocessor test next. Required initialization before the Coprocessor test is over.
- Page 95 Appendix B: AMIBIOS POST Diagnostics Error Messages Check Point Returned Next, performing the E000 option ROM had control. Initialization completed. Displaying the system configuration next. Building the multiprocessor table, if necessary. POST next. The system configuration is displayed. Uncompressing the DMI data and initializing DMI. Copying any code to specific areas.
- Page 96 BIOS Manual Notes B-10...
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