Chrontel CH7219 Application Note

Chrontel
P C B L a y o u t a n d D e s i g n G u i d e f o r C H 7 2 1 9
I
1.0
NTRODUCTION
Chrontel's CH7219 is specially designed to target the USB Type-C to HDMI converter, adapter and docking device.
The CH7219's DP/eDP receiver is compliant with the DisplayPort Specification 1.4 and Embedded DisplayPort (eDP)
Specification version 1.4. With sophisticated DisplayPort signal detection and the Lane Swap/AUX polarity inversion
logic, the CH7219 supports USB Type-C cable plug orientation switch. With internal HDCP key Integrated, the
device support HDCP 1.4 and 2.3 specifications. In the device's receiver block, which supports four DisplayPort
Main Link Lanes input with data rate running at 1.62Gbps, 2.7Gbps, 5.4Gbps or 8.1Gbps, and converted the input
signal to HDMI output up to 4Kx2k@60Hz. Leveraging the USB Power Delivery control logic, the USB billboard
module for USB device indentify and DisplayPort's unique source/sink "Link Training" routine, the CH7219 is
capable of instantly bring up the video display to the HDMI/DVI TV/Monitor when the initialization process is
completed.
This application note focuses only on the basic PCB layout and design guidelines for the CH7219. Guidelines in
component placement, power supply decoupling, grounding, input /output signal interface are discussed in this
document.
The discussion and figures presented in this document are based on the 68-pin QFN (8x8 mm) package of the
CH7219. Please refer to the CH7219 datasheet for details of the pin assignments.
2.0 C
OMPONENT
Components associated with the CH7219 should be placed as close as possible to the respective pins. The following
will describe guidelines on how to connect critical pins, as well as the guidelines for the placement and layout of
components associated with these pins.
2.1 Power Supply Decoupling
The optimal power supply decoupling is accomplished by placing a ceramic capacitor at each of the power supply
pins as shown in Figure 1. These capacitors (C1, C2, C3, C4, C6, C7, C9, C11, C12, C14, C15, C16, C17, C18, C19
C21,C23,C24,C25,C26,C27 and C28) should be connected as close as possible to their respective power and ground
pins using short and wide traces to minimize lead inductance. Whenever possible, a physical connecting trace should
connect the ground pins of the decoupling capacitors to the CH7219 ground pins, in addition to ground vias.
2.1.1 Ground Pins
The CH7219 should be connected to a common ground plane to provide a low impedance return path for the supply
currents. Whenever possible, each of the CH7219 ground pins should be connected to its respective decoupling
capacitor ground lead directly, and then connected to the ground plane through a ground via. Short and wide traces
should be used to minimize the lead inductance. Refer to Table 1 for the Ground pin assignments.
2.1.2 Power Supply Pins
There are twelve power supply pins: AVCC, DVDD, AVDDPLL, VDDS, AVDD and VDDPLL. Refer to Table 1
for the Power supply pin assignments. Refer to Figure 1 for Power Supply Decoupling.
Table 1: Power Supply Pin Assignments for the CH7219
206-1000-058 Rev. 0.1
P
LACEMENT AND
2023-10-25
D C
ESIGN ONSIDERATIONS
AN-B058
Application Note
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