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Chrontel CH7034B Application Notes

Hdtv/vga/lvds encoder
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AN-B013
Application Notes
Chrontel
PCB Layout and Design Guide for CH7034B HDTV/VGA/LVDS Encoder
1.0 I
NTRODUCTION
Chrontel CH7034B is specifically designed for a portable system that requires connections to LCD display, High
Definition Television (HDTV) or RGB (VGA) monitor. With its advanced video encoder, flexible scaling engine and
easy-to- configure audio interface, the CH7034B satisfies manufactures' product display requirements and reduces their
cost of development and time-to-market.
This application note focuses only on the basic PCB layout and design guidelines for CH7034B HDTV/VGA/LVDS
encoder. Guidelines in component placement, power supply decoupling, grounding, input /output signal interface are
discussed in this document.
The discussion and figures that follow reflect and describe connections based on the 88-pin QFN package of the
CH7034B. Please refer to the CH7034B datasheet for the details of the pin assignments.
2.0 C
P
D
C
OMPONENT
LACEMENT AND
ESIGN
ONSIDERATIONS
Components associated with the CH7034B should be placed as close as possible to the respective pins. The following
discussion will describe guidelines on how to connect critical pins, as well as describe the guidelines for the placement
and layout of components associated with these pins.
2.1
Power Supply Decoupling
The optimum power supply decoupling is accomplished by placing a 0.1μF ceramic capacitor to each of the power
supply pins as shown in Figure 1. These capacitors (C1, C2, C4, C5, C7, C8, C10, C11, C13, C14, C16, C18, C19, C22)
should be connected as close as possible to their respective power and ground pins using short and wide traces to
minimize lead inductance. Whenever possible, a physical connecting trace should connect the ground pins of the
decoupling capacitors to the CH7034B ground pins, in addition to ground vias.
2.1.1
Ground Pins
The analog and digital grounds of the CH7034B should be connected to a common ground plane to provide a low
impedance return path for the supply currents. Whenever possible, each of the CH7034B ground pins should be
connected to its respective decoupling capacitor ground lead directly, then connected to the ground plane through a
ground via. Short and wide traces should be used to minimize the lead inductance. Refer to Table 1 for the Ground pins
assignment.
2.1.2 Power Supply Pins
The power supply include AVDD, AVDD_DAC, VDDH, AVDD_PLL, VDDIO, DVDD, VDDMQ, VDDMS.
Refer toTable1 for the Power supply pins assignment. Refer to Figure 1 for Power Supply Decoupling.
206-1000-013
Rev1.4,
06/30/2020
1

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  • Page 1 2.1.1 Ground Pins The analog and digital grounds of the CH7034B should be connected to a common ground plane to provide a low impedance return path for the supply currents. Whenever possible, each of the CH7034B ground pins should be connected to its respective decoupling capacitor ground lead directly, then connected to the ground plane through a ground via.
  • Page 2 Power-on reset sequence shown in the Figure 2, should be refer to for design target of generating the ResetB signal to CH7034B by onboard RC delay. Otherwise, the Power-on Reset Function maybe not work, and the Registers can NOT be reset to the default values. For hard ware circuit, please refer to 2.3 RESETB.
  • Page 3 CHRONTEL AN-B013 AVDD <9ms Other Powers ResetB Figure 2: Power-on Reset Function’s Sequence on board ResetB signal is generate by system global reset. In this case, the power supply should be valid and stable for at least 20ms before the reset signal is valid. The pulse width of valid reset signal should be at least 100us. Otherwise, the chip can’t work well.

  • Page 4: Global Reset

    A power reset switch can be placed on the RESETB pin on the PCB as a hardware reset for CH7034B QFN or connect to the system’s global reset as shown in Figure 5. When the pin is high, the reset function can also be controlled through the serial port.
  • Page 5 CH7034B includes an oscillator circuit that allows a predefined-frequency crystal to be connected directly. Alternatively, an externally generated clock source may be supplied to CH7034B. If an external clock source is used, it should have CMOS level specifications. The clock should be connected to the XI pin, and the XO pin should be left open.

  • Page 6: Input Pins

    The resistor(R3and R4) value according to the capactive Loading. It is highly recommended to add diode(SM5817) to prevent back driver from TV or Monitor in VDD5 SPCM and SPDM for autoload Figure 7: Serial Port Interface: SPCM, SPDM and SPC, SPD pins of CH7034B Input Pins 206-1000-013 Rev1.4,...

  • Page 7: Miscellaneous Pins

     Data Inputs CH7034B can accept up to 24 data inputs, as shown in Figure 8, from a digital video port of a graphics controller. The swing is defined by VDDIO (1.2 ~ 3.3V). Unused Data input pins should be pulled low with 10kΩ resistors or shorted to Ground directly.
  • Page 8  VGA output VGA standard output signal level of Hsync and Vsync is more than 2.4V. CH7034B Hsync and Vsync output signal level is same with AVDD power supply. Customer can use 74ACT08 (AND GATE) to pull high this signal level to 5V(recommend to add the diode)..
  • Page 9 A Z5125-01H A Z5125-01H A Z5125-01H A Z5125-01H Figure 9: CH7034B YpbPr, RGB+Csync and VGA output Note: In order to minimize the hazard of ESD, a set of protection diodes (AZ5125-01H) are highly recommended for each DAC and Sync Output. 206-1000-013 Rev1.4,...
  • Page 10 Please check the panels’ power and backlight voltage specifications. ENABLK(pin58) and ENAVDD(pin57) of the CH7034B can be used as control signal to turn on the power to the LVDS backlight and the LVDS logic circuitry.
  • Page 11 CHRONTEL AN-B013 Thermal Via Array Exposed Pad (5x5) 1 mm Pitch 6.6 mm land pattern 0.3 mm diameter Figure 11: Thermal Land Pattern When applying solder paste to the thermal land pattern, the recommended stencil thickness is from 5 to 8 mils.

  • Page 12: Design Example

    EFERENCE ESIGN XAMPLE The figures below are the reference schematic of CH7034B, which is provided here for design reference only. Please contact Chrontel Applications group if necessary. Table 3 provides the BOM list for the reference schematic. Reference Schematic 206-1000-013 Rev1.4,...
  • Page 13 CHRONTEL AN-B013 (a) QFN Package 206-1000-013 Rev1.4, 06/30/2020...
  • Page 14 CHRONTEL AN-B013 (b) YpbPr, RGB+Csync and VGA output 206-1000-013 Rev1.4, 06/30/2020...
  • Page 15 CHRONTEL AN-B013 Open LDI Connector, Please reference your Panel Spec LDC0* LDC0 LDC1* LDC1 LDC2* LDC2 LLC* CLK1M CLK1P Shiel d GND reser ved ENAVDD_Panel ENAVDD_Panel reser ved reser ved PWM_panel PWM_Panel reser ved reser ved ENABLK_panel ENABLK_Panel reser ved...
  • Page 16 CHRONTEL AN-B013 Reference Board Preliminary BOM Table 3: CH7034B Reference Design BOM List Item Quantity Reference Part D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13 AZ5125-01H SM5817 C1,C2, C4, C5, C6, C7, C10, C12, C13, C15, C16, 0.1uF...

  • Page 17: Revision History

    CHRONTEL AN-B013 4.0 R EVISION ISTORY Table 4: Revisions Rev. # Date Section Description 05/24/2010 Initial release 03/10/2011 Add DDC pin Add DDC pin for LVDS output Add the frequency of PWM wave can be 16KHz, 32KHz, 64KHz, and 128KHz via register setting.
  • Page 18 CHRONTEL warrants each part to be free from defects in material and workmanship for a period of one (1) year from date of shipment. Chrontel assumes no liability for errors contained within this document. The customer should make sure that they have the most recent data sheet version.

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