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Asahi KASEI AKM AK7734 Instruction Manual

Audio dsp with 2-channel adc/src
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The AK7734 is a highly integrated audio digital signal processor with integrated 2ch 24bit ADC and 2ch SRC.
It includes internal memories for digital audio processing, that allows surround effect process, time alignment
and parametric equalizing. More over, the AK7734 can process both data and filter coefficients as floating
point data so that high accuracy IIR/FIR filter performance can be achieved easily. The internal SRC has
various sampling rate converting modes, corresponds many sampling rates without changing the DSP
operating sampling frequency. The AK7734 can operate a hands-free software by AKM, as well as sound
processing, by programs downloaded via the microprocessor interface.
[DSP Block]
- Word length: 24bit (Coefficient RAM & Data RAM: F24 floating point)
- Processing Speed: 13.6 ns (1536step/fs; fs = 48kHz)
- Multiplication: 20 x 24
- Divider 20 / 20
- ALU: 48bit arithmetic operation (overflow margin 4bit) 20bit floating point arithmetic
and logic operation
- Program RAM: 3072 x 24bit
- Coefficient RAM: 2048 x 24bit (F24 floating point)
- Data RAM: 2048 x 24-bit (F24 floating point)
- Offset Register: 64 x 13bit
- Delay RAM1: 3072 x 24-bit
- Delay RAM2: 2048 x 24-bit
- Sampling rate: fs= 7.35k ~ 48kHz
- Master Clock: 1536fs
(generated from 32fs, 48fs, 64fs, 128fs, 256fs, 384fs by internal PLL)
- Master/Slave Operation
[ADC Block]
- 64 times Over sampling
- 24bit 2ch
- Sampling rate: 7.35 ~ 48kHz
- S/(N+D): 83dB (fs = 48kHz)
- DR, S/N: 96dB (fs = 48kHz)
- Integrated DC offset canceling High Pass Filter
[SRC Block]
- 2ch x 1 system
- Support frequency: Fin = 7.35kHz ~ 96kHz
[Digital Interface Input/Output]
- 8ch Serial Data Input
- 8ch Serial Data Output
MS1033-E-03
Audio DSP with 2-Channel ADC/SRC
GENERAL DESCRIPTION
FEATURES
44-bit Double precision arithmetic available
20bit
(FSO/FSI = 0.167~ 6.0)
- 1 -
Fout = 7.35kHz ~ 48kHz
[AK7734]
AK7734
2010/06

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  • Page 1 [AK7734] AK7734 Audio DSP with 2-Channel ADC/SRC GENERAL DESCRIPTION The AK7734 is a highly integrated audio digital signal processor with integrated 2ch 24bit ADC and 2ch SRC. It includes internal memories for digital audio processing, that allows surround effect process, time alignment and parametric equalizing.
  • Page 2 [AK7734] [Micro Computer Interface] C Interface or 4-wired Interface [General] - Integrated PLL - Integrated Regulator 3.3V 1.8V - Power Supply: 3.3V ± 0.3V - Operating Temperature Range: -40˚C ~ 85˚C - 48pin LQFP MS1033-E-03 - 2 - 2010/06...
  • Page 3 [AK7734] Block Diagram VCOM AVDRV VREF AINR AINL SDOUTAD AVDD DVDD CLKOE CLKO BITCLKOE BITCLKO LRCLKOE LRCLKO LFLT Pull Down Open Drain CLKGEN & CONT I2CSEL BITCLKI1 MICIF RQN / CAD1 MLRCLK0 LRCLKI1 SI / CAD0 MBITCLK0 INITRSTN SCLK / SCL CKM[3:0] SELRDY MADCLK0...
  • Page 4 [AK7734] DLP0,DLP1 CP0,CP1 DP0,DP1 DLRAM1:3072W×24-Bit OFREG DRAM CRAM DLRAM2:2048W×24-Bit 64w×13-Bit 2048w×24-Bit 2048W×24-Bit CBU S(2 4 -Bit) DBU S(2 4 -Bit ) Micon I/F MP×24 MP×20 Control Se ria l I /F PRAM 3072w × 36-Bit Multiply 24×20 → 44-Bit Stack: 5level(max) TMP 12×24-Bit 2 4 -Bit 4 4 -Bit...
  • Page 5 [AK7734] Ordering Guide -40 ∼ +85°C AK7734XQ 48pin LQFP AKD7734 Evaluation Board for AK7734 Pin Layout SRCLFLT CLKO VSS4 BITCLKO DVDD LRCLKO CKM [3] CKM [0] SETSRC INITRSTN 48pin LQFP TESTI2 I2CSEL (TOP VIEW) AINR DVDD AINL VSS2 AVDD SDOUT1 VCOM SDOUT2 VSS5...

  • Page 6: Pin Function

    [AK7734] PIN FUNCTION Name Function Classification Test1 Pin (Internal pull-down) TESTI1 Test This pin must be connected to VSS. CKM[2] Clock Mode Select Pin2 Mode Select CKM[1] Clock Mode Select Pin1 Mode Select SDIN1 Serial Data Input Pin1 Digital Input Conditional Jump Pin0 A conditional jump pin (JX0) is available by setting control register (JX0E) to Conditional Input...
  • Page 7 [AK7734] Name Function Classification O Serial Bit Clock Output Pin System Clock 23 BITCLKO Outputs “L” during initial reset in master mode. Output O Clock Output Pin 24 CLKO Clock Output Outputs “L” during initial reset. Status Output Pin 25 STO Status Outputs “H”...
  • Page 8 [AK7734] Name Function Classification 44 AINL I ADC Single-ended Input Pin for Lch Analog Input Analog 45 AVDD I Analog Ground 0V Power Supply Analog Common Voltage Output pin Connect 0.1μF and 2.2μF capacitors between this pin and No.47 pin 46 VCOM Analog Output (VSS5).

  • Page 9: Absolute Maximum Ratings

    [AK7734] ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=VSS3=VSS4=VSS5=0V: Note Parameter Symbol Units Power Supply Voltage Analog AVDD -0.3 Digital DVDD -0.3 Input Current (except for power supply pin ) – ±10 Analog Input Voltage VINA -0.3 AVDD+0.3 AINL pin, AINR pin Digital Input Voltage VIND -0.3 DVDD+0.3...

  • Page 10: Electric Characteristics

    [AK7734] ELECTRIC CHARACTERISTICS (1) Analog Characteristics 1) ADC 1-1) fs=8kHz (Ta=25ºC; AVDD=DVDD=3.3V, BITCLK=64fs; Signal frequency 1kHz; Measurement frequency = 20Hz~3.4kHz @fs=8kHz; CKM mode0(CKM[3:0]=LLLL) Unless otherwise specified.) Parameter Units Resolution Bits Section Dynamic Characteristics S/(N+D) (-1dBFS) Dynamic Range (Note Inter-Channel Isolation (fin=1kHz) (Note DC accuracy Channel Gain Mismatch...
  • Page 11 [AK7734] (2) SRC (Ta=25ºC; AVDD = DVDD=3.3V; VSS=0V, data = 24bit; measurement bandwidth = 20Hz~ FSO/2; unless otherwise specified.) Parameter Symbol Units Resolution Bits Input Sample Rate 7.35 Output Sample Rate 7.35 THD+N (Input= 1kHz, 0dBFS) FSO/FSI=44.1kHz/48kHz -112 FSO/FSI=44.1kHz/96kHz -104 FSO/FSI=48kHz/44.1kHz -112 FSO/FSI=48kHz/96kHz...
  • Page 12 [AK7734] (4) Current Consumption (Ta=25ºC; AVDD=DVDD=3.0~3.6V (when typ=3.3V, max=3.6V)) Parameter Units Power Supply Current (Note AVDD DVDD AVDD+DVDD INITRSTN pin= “L” (reference) (Note Note 15. The current of DVDD changes depending on the system frequency and contents of the DSP program. Note 16.
  • Page 13 [AK7734] DIGITAL FILTER CHARACTERISTICS ADC Section 1. fs=8kHz (Ta=-40ºC ~85ºC, AVDD=DVDD=3.0~3.6V, fs=8kHz; Note Parameter Symbol Units Passband (±0.1dB) (Note 3.15 (-1.0dB) 3.63 (-3.0dB) 3.83 Stopband 4.66 Passband Ripple (Note ±0.1 Stopband Attenuation (Note Note μs Group Delay Distortion Group Delay (Ts=1/fs) Note 17.

  • Page 14: Switching Characteristics

    [AK7734] SWITCHING CHARACTERISTICS System Clock (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V) Parameter Symbol Units XTI CKM[3:0]=0000, 0001, 0010 a) with a Crystal Oscillator: fXTI 11.2896 CKM[3:0]=0000 fs=44.1kHz 12.288 fs=48kHz fXTI 16.9344 CKM[3:0]=0001 fs=44.1kHz 18.432 fs=48kHz b) with an External Clock Duty Cycle fXTI 11.2896 CKM[3:0]=0000, 0010 fs=44.1kHz 11.0 12.4...
  • Page 15 [AK7734] SRC Input Clock (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V; VSS=0V) Parameter Symbol Units 7.35 LRCLKI2 Frequency BITCLKI2 Frequency Frequency fBCLK 0.23 3.072 6.144 High Level Width tBCLKH Low Level Width tBCLKL Reset (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V) Parameter Symbol Units INITRSTN (Note tRST Note 28. It must be “L” when power-up the AK7734. MS1033-E-03 - 15 - 2010/06...
  • Page 16 [AK7734] Audio Interface (SDIN1-4, SDOUT1-4) (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V, CL=20pF) Parameter Symbol Units DSP Section Input SDIN1-4 (Note Delay Time from BICLKI1 “ ” to LRCLKI1 (Note Note tBLRD Delay Time from LRCLKI1 to BITCLKI1 “ ” (Note Note tLRBD Serial Data Input Latch Setup Time tBSIDS Serial Data Input Latch Hold Time tBSIDH...
  • Page 17 [AK7734] Microprocessor Interface (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V; VSS=0V; CL=20pF) Parameter Symbol Units Microprocessor Interface Signal RQN Fall Time tWRF RQN Rise Time tWRR SCLK Fall Time SCLK Rise Time SCLK Frequency fSCLK SCLK Low Level Width tSCLKL SCLK High Level Width tSCLKH Microprocessor AK7734 High Level Width...
  • Page 18 [AK7734] Timing Diagram 1/fXTI tXTI=1/fXTI 1/fXTI 1/fs ts=1/fs 1/fs LRCLKI1,2 1/fBCLK tBCLK=1/fBCLK 1/fBCLK BITCLKI1,2 tBCLKH tBCLKL Figure 3. System Clock INITRSTN tRST Figure 4. Reset Note 39. The INITRSTN pin must be “L” when power-up/power-down the AK7734. MS1033-E-03 - 18 - 2010/06...
  • Page 19 [AK7734] LRCLKI1,2 tBLRD tLRBD BITCLKI1,2 tBSIDS tBSIDH SDINn n=1,2,3,4 Figure 5. Audio Interface (DSP Section Slave Mode Input) LRCLKI2 tBLRD tLRBD BITCLKI2 tBSIDS tBSIDH SDIN4 Figure 6. Audio Interface (SRC Section Input) LRCLKI1,2 tLRD BITCLKI1,2 tBSOD tLRD tBSOD SDOUTn n=1,2,3,4 50%DVDD Figure 7.
  • Page 20 [AK7734] LRCLKO 50%DVDD tMBL tMBL BITCLKO 50%DVDD tBSIDS tBSIDH SDINn n=1,2,3,4 Figure 8. Audio Interface (Master Mode Input) LRCLKO 50%DVDD tLRD BITCLKO 50%DVDD tBSOD tLRD tBSOD SDOUTn n=1,2,3,4 50%DVDD Figure 9. Audio Interface (Master Mode Output) MS1033-E-03 - 20 - 2010/06...
  • Page 21 [AK7734] tWRF tWRR SCLK tSCLKL tSCLKH 1/fSCLK 1/fSCLK INITRSTN tRST tIRRQ Figure 10. Microprocessor Interface MS1033-E-03 - 21 - 2010/06...
  • Page 22 [AK7734] tWRQH tSIS tSIH SCLK tWSC tSCW tWSC tSCW tSCW Figure 11. Microprocessor Interface (Microprocessor AK7734) SCLK tSOH tSOS Figure 12. Microprocessor Interface (AK7734 Microprocessor) tLOW tHIGH tBUF tHD:STA tHD:DAT tSU:DAT tSU:STA tSU:STO Stop Start Start Stop Figure 13. I C Bus Interface MS1033-E-03 - 22 -...

  • Page 23: Operation Overview

    [AK7734] OPERATION OVERVIEW CKM[3:0] Clock Mode Select Pin Master/Slave mode switching, MCLK/ICLK (internal master clock/generating clock) clock source pin select, and ICLK frequency change are controlled by CKM [3:0] clock mode select pins. CKM[3:0] pins can only be set during initial reset or clock reset.
  • Page 24 [AK7734] Relationship between MCLK Generating Clock (ICLK) and MCLK ICLK REFCLK MCLK XTI Pin Divider CKM mode 0/1/2 (MCLK source) ICLK REFCLK MCLK BITCLKI1 Pin Divider CKM mode 3/4/5/9/A (MCLK source) ICLK REFCLK MCLK BITCLKI2 Pin Divider CKM mode B/C/D (MCLK source) MCLK 73.728MHz(@fs=48kHz) Figure 14.
  • Page 25 [AK7734] Slave Mode (normal) (CKM Mode 2) fs: sampling frequency Input Frequency Range Use of Crystal Mode [3:0] (MHz) Unit fs=48kHz fs=44.1kHz 0010 12.288MHz 11.2896MHz 11.0~12.4 Required System Clocks are XTI, LRCK and BITCLKI1. XTI and LRCLKI1 must be synchronized, but the phase between these clocks is not important.
  • Page 26 [AK7734] LRCLKI1 Left ch Right ch BITCLKI1 32 x BITCLK 32 x BITCLK Figure 18. CKM mode3/5 @ (DIFPCM bit = “0” & DIFI2S bit = “0”) LRCLKI1 Left ch Right ch BITCLKI1 16 x BITCLK 16 x BITCLK Figure 19. CKM mode4 @ (DIFPCM bit = “0” & DIFI2S bit = “0”) LRCLKI1 Left ch Right ch...
  • Page 27 [AK7734] Slave Mode (BITCLKI2 input, CKM Mode B-D) In CKM modeB-D, BITCLKI2 and LRCLKI2 are the master clock source instead of BITCLKI1 and LRCKKI1. CKM modeB-D can be used when not using SRC. Set SRCRST bit = “1” (SRC reset state). The master clock (MCLK) is generated from the clock input to BITCLKI2 by the internal PLL.
  • Page 28 [AK7734] CKM[3:0] Pin Setting Changing the CKM [3:0] pin settings after power-on must be execute during Initial Reset or during Clock Reset. CKM[3:0] Pin Setting / IO Interface Slave/ fs(kHz) BITCLK Mode [1:0] Master Mode [3:0] 000X 00(default) 48, 44.1 64fs 000X 32, 29.4...
  • Page 29 [AK7734] Control Register Setting The AK7734 control register settings are executed through a microcontroller interface. All registers are initialized by IRESETN pin = “L” initial reset. The system reset (SRESETN bit = “1”) does not initialize the registers. When power-up the AK7734, initial reset must always be made. Control registers CONT10, CONT11 and SRESETN, ADSMUTE, SRCSMUTE bits of CONTA can be written during the operation but all other registers must be written during system reset.
  • Page 30 [AK7734] 1. CONT0: Input Interface Select Name Default CONT0 DIFPCM DIFI2S PCM[1] PCM[0] Reserved DFS[1] DFS[0] DIFPCM: Audio interface select 0: MSB justified, LSB justified and I²S (default) 1: PCM format Note 52. When using PCM format, I²S mode can not be used. DIFI2S: Audio interface I S select 0: Except I²S mode (default)
  • Page 31 [AK7734] 2. CONT1: ADC and RAM control Name Default CONT1 ATSPAD TEST BANK[1] BANK[0] TEST SS[1] SS[0] ATSPAD: ADC soft mute transition 0: 912LRCLK(max) (19ms at fs=48kHz) (default) 1: 912LRCLK×4(max) (76ms at fs=48kHz) BANK[1:0] DLRAM mode setting DLRAM0 DLRAM1 DLRAM2 DLRAM Mode BANK[1:0] Ring 24bits...
  • Page 32 [AK7734] 3. CONT2: RAM Control Name Default CONT2 POMODE DATARAM BIT32FS WAVM WAVP[1] WAVP[0] EFEN POMODE: DLYRAM pointer0 select 0: OFREG (default) 1: DBUS direct DATARAM: DATARAM addressing select DATARAM A(000h-3FFh) B(400h-7FFh) Mode 1024word 1024word Ring addressing Ring addressing (default) Ring addressing Ring addressing Pointer...
  • Page 33 [AK7734] 4) CONT3: Input Interface /Clock Select Name Default CONT3 DIF2[1] DIF2[0] DIF1[1] DIF1[0] CLKS[2] CLKS[1] CLKS[0] DIF2[1:0]: DSP DIN2, DIN3 input format select DIF2 Mode DIF2[1:0] Input Data Format MSB justified (24Bits) (default) LSB justified 24Bits LSB justified 20Bits LSB justified 16Bits Note 58.
  • Page 34 [AK7734] 5. CONT4: Output Interface Setting Name Default CONT4 DOF3[1] DOF3[0] DOF2[1] DOF2[0] DOF1[1] DOF1[0] TEST DOF3[1:0]: DSP DOUT3, DOUT4 output format select DOF3Mode DOF3[1:0] Output Data format MSB justified (24Bits) (default) LSB justified 24Bits LSB justified 20Bits LSB justified 16Bits Note 62.
  • Page 35 [AK7734] 6. CONT5: Input/Output Setting Name Default CONT5 CLKOE BITCLKE LRCLKE OUT2E OUT1E JX1E JX0E CLKOE 0: CLKO = “L” (default) 1: CLKO Output Enable BITCLKE 0: BITCLKO = “L” (default) 1: Output Enable When the AK7734 is in slave mode, the BITCLKO output can be set to “L”. LRCLKE 0: LRCLKO = “L”...
  • Page 36 [AK7734] 7. CONT6: DSP Output Select Name Default CONT6 SELDO1[1] SELDO1[0] SELDO2[1] SELDO2[0] SELDO3[1] SELDO3[0] SELDO4 SELDO1[1:0]: SDOUT1 output select SELDO1 Mode SELDO1[1:0] Output Function DSP DOUT1 (default) SDIN1 ADC SDOUTAD DSP GP1 Note 65. The output data format of SDOUTAD at ADC section is fixed to MSB justified. SELDO2[1:0]: SDOUT2 output select SELDO2 Mode SELDO2[1:0]...
  • Page 37 [AK7734] 8. CONT7: Output Setting Name Default CONT7 WDTEN LOCKE RDYE SELRDY OUT4E OUT3E CLKOP WDTEN 0: WDTE Enable (default) 1: WDTE Disable LOCKE 0: SRC PLL LOCK Disable (default) 1: SRC PLL LOCK Enable RDYE 0: RDY Disable (default) 1: RDY Enable SELRDY 0: SO Output (default)
  • Page 38 [AK7734] 9. CONT8: Input /Output Setting Name Default CONT8 OUTS SELBCK AUTOSEL TEST TEST SELDI4 JX2E OUTS: LRCLKO and BITCLKO output select in slave mode 0: Bypass output of LRCLKI1 and BITCLKI1 via buffer. (default) 1: LRCLKI1 and BITCLKI1 are output. When BITCLKI1 is 64fs (BIT32FS bit = “0”), LRCLKO is “H”...
  • Page 39 [AK7734] 10. CONT9: SRC Setting Name Default CONT9 BIEDGE IDIF[2] IDIF[1] IDIF[0] BIFS[1] BIFS[0] SEMIAUTO BIEDGE: BITCLKI2 select when using SRC 0: Falling at LRCLKI2 edge (default) 1: Rising at LRCLKI2 edge Note 67. It is enabled only when SRC input interface is in PCM mode (IDIF mode6/7). IDIF[2:0]: SDIN4(SRCI) input interface select fsi: SRC input sampling rate IDIF Mode...
  • Page 40 [AK7734] 11. CONTA: Reset and Soft Mute SRESETN, ADSMUTE and SRCSMUTE bits can be written during RUN. Name Default CONTA SRESETN ADRST ADSMUTE SRCSMUTE TEST SRCRST CKRST SRESETN: System Reset N 0: System Reset (default) 1: System Reset release When SRESETN bit = “0”, ADC, SRC and DSP are in reset state regardless of the ADRST and SRCRST bits settings.
  • Page 41 [AK7734] 12. CONT10-11: ADC Volume Setting Name Default CONT10 VOLADL VOLADL *VOLADL *VOLADL VOLADL VOLADL VOLADL VOLADL CONT11 VOLADR VOLADR *VOLADR *VOLADR VOLADR VOLADR VOLADR VOLADR Note 70. Refer to “ADC Digital Volume”. MS1033-E-03 - 41 - 2010/06...
  • Page 42 [AK7734] Reset 1) Definition of reset state The AK7734 has three types of reset function which are Initial reset, Clock reset and System reset. Operating condition (RUN state) is defined as when these reset are released. In the Initial reset condition, the INITRSTN pin= “L” and all blocks DSP/PLL/ADC/SRC and etc.
  • Page 43 [AK7734] 4) Clock Reset CKM[3:0] pin settings and Input clock ICLK (XTI@CKM Mode 0/1/2 or BITCLK@CKM Mode 3/4/5/9/A or BITCLKI2@CKM modeB/C/D) can be also changed during the clock reset as well as during initial reset. By this reset, both the PLL and the internal clocks stop and clock selection can be safely done during System Reset. After System Reset, the AK7734 enters Clock Reset condition by setting the CKRST bit = “1”.
  • Page 44 [AK7734] 6) Protection Circuit for Regulator The AK7734 has an over-current and over-voltage protection circuits. Regulator may be shut-down by this protection circuit when the power supply of the AK7734 is unstable by an instantaneous power failure. In this case, an initial reset is required.
  • Page 45 [AK7734] Power Up Sequence 1) Initial Reset Sequence The AK7734 should be powered up at the INITRSTN pin= “L”. This initial reset initializes control resisters. The power supply sequence for AVDD and DVDD is not critical but all power supplies must be On before start operating the AK7734.
  • Page 46 [AK7734] 3) Power Down Sequence When power down the AK7734, the INITRSTN pin must be “L” and external clocks should be stopped during initial reset or system reset before power down the AK7734. Never supply any clocks to the AK7734 when powered down. AVDD DVDD INITRSTN (pin)
  • Page 47 [AK7734] Audio Data Interface Serial audio data the SDIN4 pin is connected to 2ch SRC and interfaced with external system, using LRCLKI2 and BITCLKI2 clocks. The SDIN1-3 and SDOUT1-4 pins are interfaced with external system using LRCLKI1 and BITCLKI1 in slave mode, LRCLKO and BITCLKO in master mode. The data format is 2's compliment MSB first. I/O format supports I S compatible.
  • Page 48 [AK7734] 2) Master Mode LSB Justified(24bit, 20bit, 16bit), BITCLK64fs Left ch Right ch LRCLKO BITCLKO 31 30 23 22 21 20 19 18 17 16 15 14 1 0 31 30 23 22 21 20 19 18 17 16 15 14 SDIN1-3 Don’t care 22 21 20 19...
  • Page 49 [AK7734] Left ch Right ch LRCLKI1 BITCLKI1 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 SDIN1-3 M:MSB,L:LSB 22 21 20 19 2 1 L...
  • Page 50 [AK7734] 5) Slave Mode LSB Justified(16bit), BITCLK32fs When using this mode, set all input formats to LSB-justified 16-bit and output formats to MSB-justified. LRCLKI1 BITCLKI1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 5 4 3 2 1 0 SDIN1-3 14 13 12 11...
  • Page 51 [AK7734] 7) Slave Mode MSB Justified(24bit), BITCLK64fs Left ch Right ch LRCLKI2 BITCLKI2 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 SDIN1-3 M:MSB,L:LSB 22 2120 19...
  • Page 52 [AK7734] 9) I²S Compatible: Master Mode When using this mode, set all input and output formats to MSB-justified 24-bit. Left ch Right ch LRCLKO BITCLKO 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 M:MSB,L:LSB SDIN1-3...
  • Page 53 [AK7734] 11) I²S Compatible: Slave Mode When using this mode, set all input and output formats to MSB-justified 24-bit. Left ch Right ch LRCLKI1 BITCLKI1 23 22 21 20 19 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 10 9 8 7 6 5 4 3 2 1 0 SDIN1-3 22 21 20...
  • Page 54 [AK7734] 12) PCM Format tBCLK LRCLKI1 BITCLKI1 62 61 60 59 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 22 21 20 2 1 L 22 21 20 19 2 1 L...
  • Page 55 [AK7734] tBCLK LRCLKI1 BITCLKI1 62 61 60 59 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 SDIN1-3 22 21 20 19 2 1 L 22 21 20 19 2 1 L...
  • Page 56 [AK7734] 1 ≤ tBCLKI ≤ 60 LRCLKI1 BITCLKI1 62 61 60 59 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 SDIN1-3 tBCLK 22 21 20 19 2 1 L...
  • Page 57 [AK7734] 1 ≤ tBCLK ≤ 60 LRCLKI1 BITCLKI1 62 61 60 59 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 SDIN1-3 tBCLK 22 21 20 19 2 1 L...
  • Page 58 [AK7734] Microcontroller Interface (I2CSEL= “L”) 1) Configuration The access format is: Command code(8bit) + Address + Data (MSB First) Length Command MSB bit is R/W flag. The followed 7bit indicates access area such as PRAM / CRAM / registers. Address 16 / 0 Valid only for those cases where accessed areas have addresses such as PRAM / CRAM / OFREG.
  • Page 59 [AK7734] 3) Address Address description is always LSB justified. Accessing command code BIT[6:4]= “000” to “011” requires 16bit address. Accessing command code BIT[6:4]= “100” to “111” requires no address. 4) Data Length of write data is depending on the writing area size. When accessing RAM, data may be written from sequential address locations by reading data continuously.
  • Page 60 [AK7734] 5) Echo-Back Mode The AK7734 has an Echo-back mode where written-data is output on the SO pin one after another. 1. Write don’tcare COMMAND ADDRESS1 ADDRESS2 DATA1 DATA2 (L/H) COMMAND ADDRESS1 INVALID INVALID COMMAND ADDRESS1 ADDRESS2 DATA1 COMMAND Data is output on SO delaying the time for 8bit from SI input. Figure 56.
  • Page 61 [AK7734] 6) Format [1] Write Operation during System Reset 1. Program RAM (PRAM) Writing (during System Reset) (1) COMMAND (2) ADDRESS1 0 0 0 0 0 0 0 0 (3) ADDRESS2 0 0 0 0 0 0 0 0 (4) DATA1 0 0 0 0 D35 D34 D33 D32 (5) DATA2 D31~D24...
  • Page 62 [AK7734] [3] Write Operation during Run 1. Coefficient RAM (CRAM) writing (during Run) Input (1) COMMAND 80h~8Fh (one data at 80h, sixteen data at 8Fh) (2) ADDRESS1 0 0 0 0 A11 A10 A9 A8 (3) ADDRESS2 A7~A0 (4) DATA1 D23~D16 (5) DATA2 D15~D8...
  • Page 63 [AK7734] [4] Read Operation during System Reset 1. Program RAM (PRAM) Reading (during System Reset) Input Output (1) COMMAND (2) ADDRESS1 0 0 0 0 0 0 0 0 (3) ADDRESS2 0 0 0 0 0 0 0 0 (4) DATA1 0 0 0 0 D35 D34 D33 D32 (5) DATA2 D31~D24...
  • Page 64 [AK7734] [6] Read Operation during Run 1. CRAM/OFREG Write Preparation Reading (during RUN) Input Output (1) COMMAND (2) ADDRESS1 A15~A8 (3) ADDRESS2 A8~A0 (4) DATA1 D23~D16 (5) DATA2 D15~D8 (6) DATA3 D7~D0 2. @MICR2/3/4 Reading (during RUN) Input Output (1) COMMAND 76h (MIR1 Read) 78h (MIR2 Read) 7Ah (MIR3 Read)
  • Page 65 [AK7734] [2] RAM Writing Timing during RUN Use this operation to rewrite Coefficient RAM (CRAM) and Offset REG(OFREG) during RUN. 1. Write Preparation After inputting the assigned command code (8-bit) to select the number of data from 1 to 16, input the Starting Address of write (16-bit all 0) and the number of data assigned by command code in this order.
  • Page 66 [AK7734] SCLK d on’t care don’ t car e (L/ H) (L /H) Echo back output Address DATA DATA DATA DATA DATA RDY= “H” Figure 62. CRAM, OFREG Write Preparation Confirm SRESETN= “1” SCLK Command 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 don’tcare don’tcare...
  • Page 67 [AK7734] [3] External Conditional Jump External Conditional Jump Code Writing (during System Reset and RUN) (1) COMMAND (2) DATA D7~D0 External Conditional Jump code can be input during both DSP Reset and RUN. Input data is set to the designated register on the rising edge of LRCLKO.
  • Page 68 [AK7734] SRESETN= “1” SCLK don’tcare don’tcare D7 … D0 (L/H) (L/H) L ch R ch LRCLKO max 2LRCLK max0.25LRCLK Figure 65. External Conditional Jump Timing (during RUN) [4] RAM Reading Timing during System Reset Read Program RAM (PRAM), Coefficient RAM (CRAM) and Offset REG (OFREG) during System Reset in the order of input Command code and Address.
  • Page 69 [AK7734] SRESETN (Control Register Setting is Omitted SCLK don’tcare don’tcare Command Address (L/H) (L/H) Echo Back Output DATA RDY = “H” Figure 67. RAM Reading during System Reset and RUN C Bus Interface (I2CSEL= “H”) Access to the AK7734 registers and RAM is processed by I²C bus. The format of the I²C is complement with fast mode (max: 400kHz).
  • Page 70 [AK7734] [2] Start condition and Stop Condition Start condition is generated by the transition of “H” to “L” on the SDA line while the SCL line is “H”. All instructions are initiated by Start condition. Stop condition is generated by the transition of “L” to “H” on SDA line while SCL line is “H”.
  • Page 71 [AK7734] Clock pulse for acknowledge SCL FROM MASTER DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY acknowledge RECEIVER START CONDITION Figure 71. Generation of Acknowledgement [5] The First Byte The First Byte which includes the Slave-address is input after the Start condition is set, and a target IC device that will be accessed on the bus is selected by the Slave-address.
  • Page 72 [AK7734] Example) When transferring / receiving A1B2C3 (hex) 24-bit serial data in microprocessor interface format: (1) Microcomputer interface format (1) I C format 24BIT 8BIT 8BIT 8BIT A …Acknowledge Figure 73. Division of Data Note 83. In this document, there is a case that describes a write instruction command code which is received at the second byte as “Write Command”.
  • Page 73 [AK7734] Command Address Data length Description Code 3byte × n Write preparation to CRAM during RUN. 80h-8Fh 2byte BIT3 ~ BIT0 of the command code assign # of write operation (80h:1, 81h:2,…, 8Fh: 16). Write operation exceeding the assigned # of write, abandons the data.
  • Page 74 [AK7734] 3) Read Sequence In the AK7734, when a “write- slave-address assignment” is received at the first byte, the read command at the second byte and the data at the third and succeeding bytes are received. At the data block, the address is received in a single byte unit in accordance with a read command code.
  • Page 75 [AK7734] 4) Acknowledgement Polling The AK7734 cannot receive instructions while the RDY pin (Data Write Ready pin) is at a low level. The maximum transition time of the RDY pin from low level to high level is specified in the “ Microcontroller Interface (I2CSEL= “L”)”...
  • Page 76 [AK7734] [4] When Read Slave-address assignment is received without receiving Read command code Data read in the AK7734 can be made only in the previously documented Read sequence. Data cannot be read out without receiving a read command code. In the AK7734, a “Not Acknowledged” is generated when a “Read Slave-address Assignment”...
  • Page 77 [AK7734] Note: The meaning of symbols in I C format figures. …Slave Address (7 bits) SLAD …Command Code (8 bits) …Start Condition …Repeated Star tCondition …Stop Condition …R / W bit, the lowest bit of the first byte is at write (= 0) condition, Write ( 1 bit ) …R / W bit, the lowest bit of the first byte is at read (= 1) condition, Read ( 1 bit ) …Acknowledge (1 bit) …Not Acknowledge (1 bit)
  • Page 78 [AK7734] ADC Block 1) ADC High-pass filter The AK7734 ADC has digital High Pass Filter (HPF) for DC offset cancellation. The cut-off frequency of the HPF is approximately 1Hz (at fs=48kHz). This cut-off frequency is shown below. 48kHz 44.1kHz 8kHz Sampling frequency (fs) 0.93Hz 0.86Hz...
  • Page 79 [AK7734] 3) ADC Digital Volume The AK7734 has channel-independent digital volume control ( 256 levels, 0.5dB step). ADC Lch ADC Rch Gain Level VOLADL [7:0] VOLADR [7:0] +24.0dB +23.5dB +23.0dB +0.5dB 0.0dB (default) -0.5dB -102.5dB -103.0dB Mute (-∞) Table 4. ADC Digital Volume Level Setting Transition time between set values of VOLADL[7:0] and VOLADR[7:0] bits can be selected by ATSPAD bit.
  • Page 80 [AK7734] CODE CODE CODE CODE CODE CODE CODE CODE 24.0 20h 8.0 40h -8.0 60h -24.0 80h -40.0 A0h -56.0 C0h -72.0 E0h -88.0 23.5 21h 7.5 41h -8.5 61h -24.5 81h -40.5 A1h -56.5 C1h -72.5 E1h -88.5 23.0 22h 7.0 42h -9.0 62h -25.0 82h...
  • Page 81 [AK7734] SRC Block 1) Sampling rate The AK7734 includes a stereo digital sampling rate converter (SRC). The input sampling rate is supported from 7.35kHz to 96kHz(FSI). The output sampling frequency (FSO) is 7.35kHz ~ 48kHz. When sampling rate ratio FSO/FSI is more than 1, the output sampling rate is converted to 7.35kHz ~ 48kHz.
  • Page 82 [AK7734] 2) SRC Input/Output Interface [1] Input Interface Format The SDIN4 pin is for SRC input. The SRC input port works only in slave mode. An internal system clock is created by the internal PLL using BITCLKI2 (SETSRC pin= “L”) or LRCLKI2 (SETSRC pin= “H”). The input interface format is set by control registers.
  • Page 83 [AK7734] Left ch Right ch LRCLKI2 BITCLKI2 31 30 23 22 21 20 19 18 17 16 15 14 1 0 31 30 23 22 21 20 19 18 17 16 15 14 SDIN4 Don’t care 22 21 20 19 18 17 16 15 14 Don’t care 22 21 20 19...
  • Page 84 [AK7734] tBCLK LRCLKI2 BITCLKI2 62 61 60 59 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 SDIN4 L ch R ch 22 21 20 19 2 1 L 22 21 20 19...
  • Page 85 [AK7734] [2] Output interface format The SRC output format is fixed to MSB justified 24-bit 2’s complement. It outputs a data synchronizing with internal clock LRCLKO and BITCLKO. The output sampling rate is fs=48kHz or fs=44.1kHz. I²S compatible format is available by setting a control register CONT DIFI2S bit = “1”.
  • Page 86 [AK7734] 3) Soft mute operation [1] Manual Mode The soft mute operation is performed in the digital domain of the SRC output. When SRCSMUTE bit is set to “1”, the SRC output data are attenuated by −∞ during 1024 LRCLKO cycles. When the SRCSMUTE bit is set to “0” the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 LRCLKO cycles.
  • Page 87 [AK7734] SRCRST “H” SRCSMUTE Don’t Care “L” 2205/fso(SAUTOSEL=0) @44.1kHz,48kHz 8820/fso(SAUTOSEL=1) Attenuation @44.1kHz,48kHz -∞ SRCO (1) The output data is attenuated by 0dB during 1024LRCKO cycles (1024/fso). (2) The digital output corresponding to the digital input has group delay, GD. Figure 90. Soft Mute Semi-Auto Mode 4) SRC System Reset Bringing the SRCRST bit = “1”...
  • Page 88 [AK7734] External clocks Input Clocks Don’t car (No Clock) (Input port) SRCI (Don’t care) Input Data Don’t car External clocks Output Clocks (Don’t care) Don’t car (Output port) < 200ms(SETSRC pin = “H”) SRCRST < 50ms(SETSRC pin = “L”) PLL lock & Normal Power-down Power-down...
  • Page 89 [AK7734] 6) SRCPLL [1] SETSRC Pin The SETSRC pin selects a locked clock of SRCPLL. Normally this setting is fixed. PLL lock can be applied to BITCLKI2 when CONT9 BIFS[1:0] setting is 32fsi, 64fsi or 128fsi. SETSRC Mode SETSRC pin PLL Lock Pin BITCLKI2 LRCLKI2 [2] SRC PLL Loop Filter...

  • Page 90: System Design

    [AK7734] SYSTEM DESIGN 1) I2CSEL= “L” AVDD 3.3V DVDD 3.3V 10μ 10μ 1 μ 0.1μ MODE 0.1μ 2. 2μ 0.1μ 1μ TESTI1 AVDRV CKM[2] VSS3 Mode 0.1μ 10μ CKM[1] DVDD SDIN1 SCLK Jump Micom JX0/SDIN2 48pin LQFP JX1/SDIN3 Audio I/F (TOP VIEW) BITCLKI1 CLOCK...
  • Page 91 [AK7734] 2) I2CSEL= “H” AVDD 3.3V DVDD 3.3V 10μ 10μ 1 μ 0.1μ MODE 0.1μ 2. 2μ 0.1μ 1μ TESTI1 AVDRV CKM[2] VSS3 Mode 0.1μ 10μ CKM[1] DVDD SDIN1 Jump Micom JX0/SDIN2 48pin LQFP JX1/SDIN3 CAD0 Audio I/F (TOP VIEW) BITCLKI1 CAD1 CLOCK...
  • Page 92 [AK7734] (2) Peripheral Circuits 1) Ground and Power Supply To minimize digital noise coupling, AVDD and DVDD should be individually de-coupled at the AK7734. System analog power is supplied to AVDD. VSS1-5 should be connected to the same analog ground. Decoupling capacitors, particularly ceramic capacitors of small capacity, should be connected at positions as close as possible to the AK7734.
  • Page 93 [AK7734] 2.00Vpp +10V -10V Figure 97. Input Buffer Circuit (single-ended) 4) Cristal Oscillator The resistor and capacitor values for the oscillator RC circuit are shown in Table CKM Mode R1 max C0 max XTI, XTO pin Capacity 22pF 10pF or 15pF Table 10.
  • Page 94 [AK7734] PACKAGE 48pin LQFP (Unit: mm) 1.60MAX 9.00 ± 0.20 0.10 ± 0.07 7.00 1.4TYP 0.17 ± 0.05 0.19 ± 0.05 0.50 0.10 M 1.00 0˚ ~ 10˚ 0.50 ± 0.20 0.10 S Materials and Lead Specification Package: Epoxy Lead frame: Copper Lead-finish: Soldering (Pb free) plate...

  • Page 95: Revision History

    [AK7734] MARKING AK7734XQ XXXXXXX 1) Pin #1 indication 2) Date Code: XXXXXXX(7digits) 3) Marking Code: AK7734XQ 4) Asahi Kasei Logo REVISION HISTORY Date Revision Reason Page Contents (YY/MM/DD) 09/03/24 First Edition 09/11/16 Description 6, 7 Digital Ground 0V Ground 0V...

  • Page 96: Important Notice

    ” These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products.

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