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Asahi KASEI AK4588 Manual

2/8-channel audio codec with dir
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ASAHI KASEI
The AK4589 is a single chip CODEC that includes two channels of ADC and eight channels of DAC. The
ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit
architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit
architecture, and achieves wider dynamic range and lower outband noise. The AK4589 has a dynamic
range of 102dB for ADC, 114dB for DAC and is well suited for digital surround for home theater audio.
The AK4589 also has the balance volume control corresponding to the Dolby Digital (AC-3) system.
The also has digital audio receiver (DIR) and transmitter (DIT) compatible with 192kHz, 24bits. The DIR
has 8-channel input selector and can automatically detect a Non-PCM bit stream. The AK4589 provides
a compatibility of hardware and software with the AK4588.
*Dolby Digital (AC-3) is a trademark of Dolby Laboratories.
ADC/DAC part
• 2ch 24bit ADC
• 8ch 24bit DAC
• High Jitter Tolerance
• Extenal Master Clock Input:
MS0339-E-00
2/8-Channel Audio CODEC with DIR
GENERAL DESCRIPTION
FEATURES
- 64x Oversampling
- Sampling Rate up to 96kHz
- Linear Phase Digital Anti-Alias Filter
- Single-Ended Input
- S/(N+D): 92dB
- Dynamic Range, S/N: 102dB
- Digital HPF for offset cancellation
- Overflow flag
- 128x Oversampling
- Sampling Rate up to 192kHz
- 24bit 8 times Digital Filter
- Differential Outputs
- On-chip Switched-Capacitor Filter
- S/(N+D): 94dB
- Dynamic Range, S/N: 114dB
- Individual channel digital volume with 128 levels and 0.5dB step
- Soft mute
- De-emphasis for 32kHz, 44.1kHz, 48kHz
- Zero Detect Function
- 256fs, 384fs, 512fs (fs=32kHz ∼ 48kHz)
- 128fs, 192fs, 256fs (fs=64kHz ∼ 96kHz)
- 128fs (fs=120kHz ∼ 192kHz)
- 1 -
[AK4589]
AK4589
2004/09

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Summary of Contents for Asahi KASEI AK4588

  • Page 1 The also has digital audio receiver (DIR) and transmitter (DIT) compatible with 192kHz, 24bits. The DIR has 8-channel input selector and can automatically detect a Non-PCM bit stream. The AK4589 provides a compatibility of hardware and software with the AK4588. *Dolby Digital (AC-3) is a trademark of Dolby Laboratories.
  • Page 2 C Bus µP I/F for mode setting 4-wire Serial and I Operating Voltage: 4.75 to 5.25V with 5V tolerance Power Supply for output buffer: 2.7 to 5.25V 80pin LQFP Package (0.5mm pitch) AK4588 compatible w/o analog outputs MS0339-E-00 2004/09 - 2 -...
  • Page 3 ASAHI KASEI [AK4589] Block Diagram PVSS PVDD X'tal Clock Oscillator 8 to 3 Recovery Clock MCKO1 Generator Input MCKO2 Selector LRCK2 DAIF Audio BICK2 Decoder SDTO2 DAUX2 AVDD AVSS DVDD Error & CCLK Q-subcode DVSS AC-3/MPEG µP I/F STATUS buffer...
  • Page 4 ASAHI KASEI [AK4589] Ordering Guide -10 ∼ +70°C AK4589VQ 80pin LQFP(0.5mm pitch) AKD4589 Evaluation Board for AK4589 Pin Layout TEST1 INT1 BOUT TVDD DVDD AVSS DVSS AVDD VREFH VCOM (Top View) TEST3 MCKO2 MCKO1 ROUT1+ COUT ROUT1- UOUT LOUT1+ VOUT...
  • Page 5 #35 - #50 Power Supply voltage Min=4.5V, Max=5.5V Min=4.75V, Max=5.25V (*) The AK4589 has two register maps including ADC/DAC part (compatible with the AK4588) and DIR/DIT part (compatible with AK4588). Each register is selected by Chip Address. MS0339-E-00 2004/09 - 5 -...
  • Page 6 ASAHI KASEI [AK4589] PIN/FUNCTION Pin Name Function INT1 Interrupt 1 Pin Block-Start Output Pin for Receiver Input BOUT “H” during first 40 flames. TVDD Output Buffer Power Supply Pin, 2.7V∼5.25V DVDD Digital Power Supply Pin, 4.75V∼5.25V DVSS Digital Ground Pin...
  • Page 7 ASAHI KASEI [AK4589] Pin Name Function Power-Down Mode Pin When “L”, the AK4589 is powered-down, all digital output pins go “L”, all registers are reset. When CAD1/0 pins are changed, the AK4589 should be reset by PDN pin. Master Mode Select Pin MASTER “H”: Master mode, “L”: Slave mode...
  • Page 8 ASAHI KASEI [AK4589] Pin Name Function AVDD Analog Power Supply Pin, 4.75V∼5.25V Analog Ground Pin, 0V AVSS Receiver Channel 0 Pin (Internal biased pin. Internally biased at PVDD/2) No Connect pin No internal bonding. This pin should be connected to PVSS.
  • Page 9 ASAHI KASEI [AK4589] Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name Setting Analog RX0-7, LOUT1-4, ROUT1-4, LIN, RIN These pins should be open. INT0-1, BOUT, XTO, MCKO1-2, COUT, UOUT, These pins should be open.
  • Page 10 ASAHI KASEI [AK4589] ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS, PVSS=0V; Note 1) Parameter Symbol Units Power Supplies Analog AVDD -0.3 Digital DVDD -0.3 PVDD -0.3 Output buffer TVDD -0.3 ∆GND1 |AVSS-DVSS| (Note 2) ∆GND2 |AVSS-PVSS| (Note 2) ±10 Input Current (any pins except for supplies)
  • Page 11 ASAHI KASEI [AK4589] ANALOG CHARACTERISTICS (Ta=25°C; AVDD, DVDD, PVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz; 20Hz~40kHz at fs=192kHz, unless otherwise specified) Parameter Units ADC Analog Input Characteristics Resolution Bits S/(N+D) (-0.5dBFS)
  • Page 12 ASAHI KASEI [AK4589] Notes: 5. S/N measured by CCIR-ARM is 96dB(@fs=48kHz). 6. For AC-load. 4kΩ for DC-load 7. PSR is applied to AVDD, DVDD, PVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held a constant voltage. 8. S/N measured by CCIR-ARM is 102dB(@fs=48kHz).
  • Page 13 ASAHI KASEI [AK4589] DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD, PVDD=4.75∼5.25V; TVDD=2.7∼5.25V) Parameter Symbol Units High-Level Input Voltage (Except XTI pin) (XTI pin) 70%DVDD Low-Level Input Voltage (Except XTI pin) (XTI pin) 30%DVDD Input Voltage at AC Coupling (XTI pin) (Table 15)
  • Page 14 ASAHI KASEI [AK4589] SWITCHING CHARACTERISTICS (ADC/DAC part) (Ta=25°C; AVDD, DVDD, PVDD=4.75∼5.25V; TVDD=2.7∼5.25V; C =20pF) Parameter Symbol Units Master Clock Timing Master Clock 256fsn, 128fsd: fCLK 8.192 12.288 Pulse Width Low tCLKL Pulse Width High tCLKH 384fsn, 192fsd: fCLK 12.288 18.432...
  • Page 15 ASAHI KASEI [AK4589] Parameter Symbol Units Audio Interface Timing (Slave Mode) Normal mode BICK1 Period tBCK BICK1 Pulse Width Low tBCKL Pulse Width High tBCKH LRCK1 Edge to BICK1 “↑” (Note 19) tLRB BICK1 “↑” to LRCK1 Edge (Note 19)
  • Page 16 ASAHI KASEI [AK4589] Timing Diagram(ADC/DAC part) 1/fCLK MCLK tCLKH tCLKL 1/fsn, 1/fsd, 1/fsq LRCK1 tBCK BICK1 tBCKH tBCKL Clock Timing (Normal mode) 1/fCLK MCLK tCLKH tCLKL 1/fs LRCK1 tLRH tLRL tBCK BICK1 tBCKH tBCKL Clock Timing (TDM 256 mode, TDM 128 mode)
  • Page 17 ASAHI KASEI [AK4589] LRCK1 tBLR tLRB BICK1 tLRS tBSD SDTO1 50%TVDD tSDS tSDH SDTI Audio Interface Timing (Normal mode) LRCK1 tBLR tLRB BICK1 tBSD SDTO1 50%TVDD tSDS tSDH SDTI Audio Interface Timing (TDM 256 mode, TDM 128 mode) MS0339-E-00 2004/09...
  • Page 18 ASAHI KASEI [AK4589] LRCK1 50%TVDD tMBLR 50%TVDD BICK1 tBSD 50%TVDD SDTO1 tDXS tDXH DAUX1 Audio Interface timing (Master Mode) MS0339-E-00 2004/09 - 18 -...
  • Page 19 ASAHI KASEI [AK4589] SWITCHING CHARACTERISTICS (DIR/DIT part) (Ta=25°C; DVDD, AVDD, PVDD4.75~5.25V, TVDD=2.7~5.25V; C =20pF) Parameter Symbol Units Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 24.576 External Clock Frequency fECLK 11.2896 24.576 Duty dECLK MCKO1 Output Frequency fMCK1 4.096 24.576...
  • Page 20 ASAHI KASEI [AK4589] Timing Diagram(DIR/DIT part) 1/fECLK tECLKH tECLKL dECLK = tECLKH x fECLK x 100 = tECLKL x fECLK x 100 1/fMCK1 MCKO1 50%TVDD tMCKH1 tMCKL1 dMCK1 = tMCKH1 x fMCK1 x 100 = tMCKL1 x fMCK1 x 100...
  • Page 21 ASAHI KASEI [AK4589] LRCK2 50%TVDD tMBLR 50%TVDD BICK2 tBSD 50%TVDD SDTO2 tDXS tDXH DAUX2 Serial Interface Timing (Master Mode) Power Down & Reset Timing MS0339-E-00 2004/09 - 21 -...
  • Page 22 23. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. 24. I C is a registered trademark of Philips Semiconductors. Purchase of Asahi Kasei Microsystems Co., Ltd I C components conveys a license under the Philips C patent to use the components in the I C system, provided the system conform to the I specifications defined by Philips.
  • Page 23 ASAHI KASEI [AK4589] Timing Diagram (ADC/DAC part and DIR/DIT part) tCSS tCCK tCCKL tCCKH CCLK tCDH tCDS CDTI Hi-Z CDTO WRITE/READ Command Input Timing in 4-wire serial mode The ADC/DAC part doesn’t support READ command. tCSW tCSH CCLK CDTI Hi-Z...
  • Page 24 ASAHI KASEI [AK4589] tCSW tCSH CCLK CDTI tCCZ CDTO 50%TVDD READ Data Input Timing 2 in 4-wire serial mode The ADC/DAC part doesn’t support READ command. tBUF tLOW tHIGH tHD:STA tHD:DAT tSU:DAT tSU:STA tSU:STO Stop Start Start Stop C Bus mode Timing The ADC/DAC part doesn’t support READ command.
  • Page 25 ASAHI KASEI [AK4589] OPERATION OVERVIEW (ADC/DAC part) System Clock The external clocks, which are required to operate the AK4589, are MCLK, LRCK1 and BICK1. MCLK should be synchronized with LRCK1 but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit = “0”: Default), the sampling speed is set by DFS1-0 bit (Table 1).
  • Page 26 ASAHI KASEI [AK4589] LRCK1 MCLK (MHz) BICK1 (MHz) 128fs 192fs 256fs 64fs 176.4kHz 22.5792 11.2896 192.0kHz 24.5760 12.2880 Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode) (Note: At Quad speed mode (DFS1= “1”, DFS0 = “0”) are not available for ADC.)
  • Page 27 ASAHI KASEI [AK4589] Master mode and Slave mode Master Mode can be selected by setting MASTER pin to “H”. LRCK1 and BICK1 will be outputs in Master Mode. And, Slave Mode can be selected by setting this pin to “L”. LRCK1 and BICK1 will be inputs in Slave Mode.
  • Page 28 ASAHI KASEI [AK4589] Mode MASTER TDM 1 TDM0 DIF1 DIF0 SDTO1 SDTI1 LRCK1 BICK1 ↑ 24bit, M J 20bit, L J 256fs ↑ 24bit, M J 24bit, L J 256fs ↑ 24bit, M J 24bit, M J 256fs ↓ 24bit, I...
  • Page 29 ASAHI KASEI [AK4589] LRCK1 BICK1(64fs) SDTO1(o) 12 11 10 23 22 12 11 10 SDTI(i) Don’t Care Don’t Care SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0,4 Timing LRCK1 BICK1(64fs) SDTO1(o) 16 15 14 23 22...
  • Page 30 ASAHI KASEI [AK4589] 256 B ICK LRCK1 (m ode 8) LRCK1 (m ode 12) BICK1(256fs) SDTO1(o) 32 B ICK 32 B ICK SDT I1(i) 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK 32 B ICK...
  • Page 31 ASAHI KASEI [AK4589] 128 B ICK LRCK1 (m ode 16) LRCK1 (m ode 20) BICK1(128fs) SDTO1(o) 32 B ICK 32 B ICK SDT I1(i) 32 B ICK 32 B ICK 32 B ICK 32 B ICK SDT I2(i) 32 B ICK...
  • Page 32 ASAHI KASEI [AK4589] 128 B ICK LRCK1 (m ode 19) LRCK1 (m ode 23) BICK1(128fs) SDTO1(o) 32 B ICK 32 B ICK SDT I1(i) 32 B ICK 32 B ICK 32 B ICK 32 B ICK SDT I2(i) 32 B ICK...
  • Page 33 ASAHI KASEI [AK4589] Overflow Detection The AK4589 has overflow detect function for analog input. Overflow detect function is enable if OVFE bit is set to “1”. OVF pin goes to “H” if analog input of Lch or Rch overflows (more than -0.3dBFS). OVF output for overflowed analog input has the same group delay as ADC (GD = 16/fs = 333µs @fs=48kHz).
  • Page 34 ASAHI KASEI [AK4589] Digital Attenuator The AK4589 has channel-independent digital attenuator (128 levels, 0.5dB step). Attenuation level of each channel can be set by each ATT7-0 bits (Table 15). ATT7-0 Attenuation Level Default -0.5dB -1.0dB -62.5dB -63dB MUTE (-∞) MUTE (-∞) MUTE (-∞)
  • Page 35 ASAHI KASEI [AK4589] Soft mute operation Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by -∞ during ATT_DATA×ATT transition time (Table 16) from the current ATT level. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT...
  • Page 36 ASAHI KASEI [AK4589] Power ON/OFF Sequence The ADC and DACs of AK4589 are placed in the power-down mode by bringing PDN pin “L” and both digital filters are reset at the same time. PDN pin “L” also reset the control registers to their default values. In the power-down mode, the analog outputs go to VCOM voltage and DZF1-2 pins go to “L”.
  • Page 37 ASAHI KASEI [AK4589] Reset Function When RSTN1 bit = “0”, ADC and DACs are powered-down but the internal register are not initialized. The analog outputs go to VCOM voltage, DZF1-2 pins go to “H” and SDTO1 pin goes to “L”. Because some click noise occurs, the analog output should muted externally if the click noise influences system application.
  • Page 38 ASAHI KASEI [AK4589] DAC partial Power-Down Function All DACs of The AK4589 can be powered-down individually by PD1-4 bits. The analog part of DAC is in power-down by PD1-4 bits =”1”, however, the digital part is not in power-down by it. Even if all DACs were set in power-down by the partial power-down bits, the digital part continue to function.
  • Page 39 ASAHI KASEI [AK4589] Register Map Addr Register Name Control 1 TDM1 TDM0 DIF1 DIF0 SMUTE Control 2 CKS1 DFS1 LOOP1 LOOP0 SDOS DFS0 ACKS CKS0 LOUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ROUT1 Volume Control ATT7...
  • Page 40 ASAHI KASEI [AK4589] Addr Register Name Control 2 CKS1 DFS1 LOOP1 LOOP0 SDOS DFS0 ACKS CKS0 Default ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0 bits are ignored.
  • Page 41 ASAHI KASEI [AK4589] Addr Register Name LOUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ROUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 LOUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ROUT2 Volume Control...
  • Page 42 ASAHI KASEI [AK4589] Addr Register Name ATT speed ATS1 ATS0 RSTN1 & Power Down Control Default RSTN1: Internal timing reset 0: Reset. DZF1-2 pins go to “H”, but registers are not initialized. 1: Normal operation ATS1-0: Digital attenuator transition time setting (see Table 16) Initial: “00”, mode 0...
  • Page 43 ASAHI KASEI [AK4589] OPERATION OVERVIEW (DIR/DIT part) Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection The AK4589 has a Non-PCM steam auto-detection function. When the 32bit mode Non-PCM preamble based on Dolby “AC-3 Data Stream in IEC60958 Interface” is detected, the AUTO bit goes “1”. The 96bit sync code consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F.
  • Page 44 ASAHI KASEI [AK4589] Clock Source The following circuits are available to feed the clock to XTI pin of AK4589. 1) X’tal 25kΩ (typ) AK4589 Figure 17. X’tal mode Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF) 2) External clock - Note: Input clock must not exceed DVDD.
  • Page 45 ASAHI KASEI [AK4589] Sampling Frequency and Pre-emphasis Detection The AK4589 has two methods for detecting the sampling frequency as follows. 1. Clock comparison between recovered clock and X’tal oscillator 2. Sampling frequency information on channel status Those could be selected by XTL1, 0 bits. And the detected frequency is reported on FS3-0 bits.
  • Page 46 ASAHI KASEI [AK4589] De-emphasis Filter Control The AK4589 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter corresponding to four sampling frequencies (32kHz, 44.1kHz, 48kHz and 96kHz). When DEAU bit=“1”, the de-emphasis filter is enabled automatically by sampling frequency and pre-emphasis information in the channel status. The AK4589 goes this mode at default. Therefore, in Parallel Mode, the AK4589 is always placed in this mode and the status bits in channel 1 control the de-emphasis filter.
  • Page 47 ASAHI KASEI [AK4589] Biphase Input and Through Output Eight receiver inputs (RX0-7) are available in Serial Control Mode. Each input includes amplifier corresponding to unbalance mode and can accept the signal of 200mV or more. IPS2-0 bits selects the receiver channel. When BCU bit = “1”, the Block start signal, C bit and U bit can output from each pins.
  • Page 48 ASAHI KASEI [AK4589] Biphase Output The AK4589 can output either the through output(from DIR) or transmitter output(DIT; the data from DAUX2 is transformed to IEC60958 format.) from TX1/0 pins. Those could be selected by DIT bit. The source of the through output from TX0 could be selected among RX0-8 by OPS00,01 and 02 bits, for TX1, by OPS10,11 and 12 bits respectively.
  • Page 49 ASAHI KASEI [AK4589] Biphase signal input/output circuit 0.1uF 75Ω Coax 75Ω AK4589 Figure 23. Consumer Input Circuit (Coaxial Input) Note: In case of coaxial input, if a coupling level to this input from the next RX input line pattern exceeds 50mV, there is a possibility to occur an incorrect operation. In this case, it is possible to lower the coupling level by adding this decoupling capacitor.
  • Page 50 ASAHI KASEI [AK4589] Q-subcode buffers The AK4589 has Q-subcode buffer for CD application. The AK4589 takes Q-subcode into registers by following conditions. 1. The sync word (S0,S1) is constructed at least 16 “0”s. 2. The start bit is “1”. 3. Those 7bits Q-W follows to the start bit.
  • Page 51 ASAHI KASEI [AK4589] Error Handling There are the following eight events that make INT0/1 pins “H”. INT0/1 pins show the status of following conditions. 1. UNLOCK: “1” when the PLL loses lock. The AK4589 loses lock when the distance between two preambles is not correct or when those preambles are not correct.
  • Page 52 ASAHI KASEI [AK4589] Error (Error) (UNLOCK, PAR,..) INT0 pin Hold Time (max: 4096/fs) INT1 pin Hold Time = 0 Register Hold ”1” Reset (PAR,CINT,QINT) Register (others) Command READ 06H MCKO,BICK2,LRCK2 (UNLOCK) Free Run (fs: around 20kHz) MCKO,BICK2,LRCK2 (except UNLOCK) SDTO2 (UNLOCK)
  • Page 53 ASAHI KASEI [AK4589] PDN pin ="L" to "H" Initialize Read 06H INT0/1 pin ="H" Release Mute DA C output Muting Read 06H (Each Error Handling) Read 06H (Res ets registers) INT0/1 pin ="H" Figure 30. Error Handling Sequence Example 1...
  • Page 54 ASAHI KASEI [AK4589] PDN pin ="L" to "H" Initialize Read 06H INT1 pin ="H" Read 06H Detect QSUB= “1” (Read Q-buffer) New data QCRC = “0” is invalid INT1 pin ="L" New data is valid Figure 31. Error Handling Sequence Example 2 (for Q/CINT)
  • Page 55 ASAHI KASEI [AK4589] Audio Serial Interface Format The DIF0, DIF1 and DIF2 pins can select eight serial data formats as shown in Table 29. In all formats the serial data is MSB-first, 2's complement format. The SDTO2 is clocked out on the falling edge of BICK2 and the DAUX2 is latched on the rising edge of BICK2.
  • Page 56 ASAHI KASEI [AK4589] LRCK2 BICK2 (0:64fs) SDTO2 15:MSB, 0:LSB Lch Data Rch Data Figure 33. Mode 0 Timing LRCK2 BICK2 (0:64fs) SDTO2 23:MSB, 0:LSB Lch Data Rch Data Figure 34. Mode 3 Timing LRCK2 BICK2 (64fs) 23 22 23 22...
  • Page 57 ASAHI KASEI [AK4589] Register Map Addr Register Name & Power Down CS12 OCKS1 OCKS0 RSTN2 Control Format & De-em Control DIF2 DIF1 DIF0 DEAU DEM1 DEM0 Input/ Output Control 0 TX1E OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00 Input/ Output Control 1...
  • Page 58 ASAHI KASEI [AK4589] Register Definitions Reset & Initialize Addr Register Name 00H CLK & Power Down Control CS12 OCKS1 OCKS0 RSTN2 Default RSTN2: Timing Reset & Register Initialize 0: Reset & Initialize 1: Normal Operation PWN: Power Down 0: Power Down...
  • Page 59 ASAHI KASEI [AK4589] Input/Output Control Addr Register Name 02H Input/ Output Control 0 TX1E OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00 Default OPS02-00: Output Through Data Select for TX0 pin OPS12-10: Output Through Data Select for TX1 pin TX0E: TX0 Output Enable 0: Disable.
  • Page 60 ASAHI KASEI [AK4589] Mask Control for INT0 Addr Register Name 04H INT0 MASK MQI0 MAT0 MCI0 MUL0 MDTS0 MPE0 MAN0 MPR0 Default MPR0: Mask Enable for PAR bit MAN0: Mask Enable for AUDN bit MPE0: Mask Enable for PEM bit...
  • Page 61 ASAHI KASEI [AK4589] Receiver Status 0 Addr Register Name 06H Receiver status 0 QINT AUTO CINT UNLCK DTSCD AUDION Default PAR: Parity Error or Biphase Error Status 0:No Error 1:Error It is “1” if Parity Error or Biphase Error is detected in the sub-frame.
  • Page 62 ASAHI KASEI [AK4589] Receiver Channel Status Addr Register Name 08H RX Channel Status Byte 0 09H RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17...
  • Page 63 ASAHI KASEI [AK4589] Q-subcode Buffer Addr Register Name 16H Q-subcode Address / Control 17H Q-subcode Track 18H Q-subcode Index 19H Q-subcode Minute 1AH Q-subcode Second 1BH Q-subcode Frame 1CH Q-subcode Zero 1DH Q-subcode ABS Minute 1EH Q-subcode ABS Second 1FH Q-subcode ABS Frame...
  • Page 64 ASAHI KASEI [AK4589] Burst Preambles in non-PCM Bitstreams sub-frame of IEC958 11 12 27 28 29 30 31 preamble Aux. MSB V U C P 16 bits of bitstream Pa Pb Pc Pd Burst_payload stuffing repetition time of the burst Figure 37.
  • Page 65 ASAHI KASEI [AK4589] Bits of Pc Value Contents Repetition time of burst in IEC60958 frames data type ≤4096 NULL data Dolby AC-3 data 1536 reserved PAUSE MPEG-1 Layer1 data MPEG-1 Layer2 or 3 data or MPEG-2 without extension 1152 MPEG-2 data with extension...
  • Page 66 ASAHI KASEI [AK4589] Non-PCM Bitstream timing 1) When Non-PCM preamble is not coming within 4096 frames, PDN pin Bit stream Repetition time >4096 frames AUTO bit Pc Register “0” Pd Register “0” Figure 38. Timing example 1 2) When Non-PCM bitstream stops (when MULK0=0),...
  • Page 67 OPERATION OVERVIEW (ADC/DAC part, DIR/DIT part) Serial Control Interface The AK4589 has two registers, which are ADC/DAC part (AK4588 compatible) and DIR/DIT part (AK4588 compatible). Each register is set by chip address pin. (1) 4-wire serial control mode (I2C pin = “L”) The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI &...
  • Page 68 ASAHI KASEI [AK4589] (2) I C bus control mode (I2C pin = “H”) AK4589 supports the standard-mode I C-bus (max: 100kHz). Then AK4589 does not support a fast-mode I C-bus system (max: 400kHz). (2)-1 Data transfer All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4589 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the SDA line.
  • Page 69 ASAHI KASEI [AK4589] (2)-1-3 ACKNOWLEDGE ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the acknowledge clock pulse so that that it remains stable “L” during “H” period of this clock pulse. The AK4589 will generates an acknowledge after each byte has been received.
  • Page 70 ASAHI KASEI [AK4589] (2)-2 WRITE Operations Set R/W bit = “0” for the WRITE operation of the AK4589. After receipt the start condition and the first byte, the AK4589 generates an acknowledge, and awaits the second byte (register address). The second byte consists of the address for control registers of AK4589. The format is MSB first, and those most significant 3-bits are “Don’t care”.
  • Page 71 ASAHI KASEI [AK4589] (2)-3 READ Operations Set R/W bit = “1” for the READ operation of the AK4589. After transmission of a data, the master can read next address’s data by generating the acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically.
  • Page 72 ASAHI KASEI [AK4589] SYSTEM DESIGN Figure 50 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Condition: I C serial control mode Micro (S/PDIF Controller S/PDIF out...
  • Page 73 ASAHI KASEI [AK4589] 1. Grounding and Power Supply Decoupling The AK4589 requires careful attention to power supply and grounding arrangements. AVDD, DVDD, PVDD and TVDD are usually supplied from analog supply in system. Alternatively if AVDD, DVDD, PVDD and TVDD are supplied separately, the power up sequence is not critical.
  • Page 74 ASAHI KASEI [AK4589] 5. Analog Outputs Figure 51 shows an example of the Non-inverted differential output buffer and the summing amp with LPF. NJM5534D are op-amps that has low noise and +/- 15V power supply operation. 3.3n 100u 0.1u AOUTL- 3.9n...
  • Page 75 ASAHI KASEI [AK4589] PACKAGE 80-pin LQFP ( Unit : mm ) 14.0±0.2 12.0±0.2 0° ~ 10° 0.20±0.1 0.50 0.08 1.25TYP 0.50±0.1 0.10 Material & Lead finish Package: Epoxy Lead-frame: Copper Lead-finish Soldering (Pb free) plate MS0339-E-00 2004/09 - 75 -...
  • Page 76 • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein.

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Ak4589