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3.5 CHIPSET FEATURES SETUP
When you select the "CHIPSET FEATURES SETUP" on the main program, the screen
display will appears as:
Chipset Features Setup Screen
CMOS Setup Utility – Copyright © 1984-2000 Award Software
SDRAM CAS Latency Time
SDRAM Cycle Time Tras/Trc
SDRAM RAS-to -CAS
SDRAM RAS Precharge Time
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
CPU Latency Timer
Delayed Transaction
AGP Graphics Aperture Size
Use VGA BIOS in VBU Block
Power-Supply Type
On-Chip Video window size
á â à Move Enter: Select
F5: Previous Values F6: Fail-Safe Defaults
SDRAM CAS Latency Time: When synchronous DRAM is installed, the number of clock
cycles of CAS latency depends on the DRAM timing. Do not reset this field from the
default value specified by the system designer.
SDRAM Cycle Time Tras/Trc: This item allows you to select the SCLKs for an access
cycle. The settings are 7/9.
SDRAM RAS to CAS Delay: This field lets you insert a timing delay between the CAS and
RAS strobe signals, used when DRAM is written to, read from, or refreshed. Fast gives
faster performance; and Slow gives more stable performance. This field applies only when
synchronous DRAM is installed in the system.
SDRAM RAS Precharge Time: If an insufficient number of cycles is allowed for the RAS
to accumulate its charge before DRAM refresh, the refresh may be incomplete and the
DRAM may fail to retain data. Fast gives faster performance; and Slow gives more stable
Advanced Chipset Features
3
7/9
3
3
Enabled
Disabled
Disabled
Enabled
Enabled
64MB
Enabled
AT
64MB
+/-/PU/PD: Value
~27~
Menu Level
F10: Save Esc: Exit F1: General Help
F7: Optimized Defaults
AWARD BIOS SETUP
Item Help
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