LG 50PX950-AA Service Manual page 32

Block Diagram – 3DF B/D
5V_VCC
3D_SYNC
I2C
L/R DETECT
BCM
FPGA RESET
LVDS 2Ch
■ Input
(PDP 3DTV)
5V_VCC
X-tal
(54MHz)
I2C
L/R DETECT
FPGA RESET
LVDS 2Ch
EP3C55F484
1 LVDS RX (2 channel)
10 bit 1920x1080p@60Hz
PROM
(16Mbit)
I2C
2D to 3D
Converter
FPGA RESET
(FPGA)
LVDS 2Ch
■ Processing
148.5 MHz, 74.24 MHz
DDR2 IF(153MHz)
CSC (RGB YUV) included
Scaler included
I2C input from LVDS RX
X-tal PROM
(54MHz) (16Mbit)
LVDS 2Ch
(Left)
3D Formatter
(FPGA)
EP3C55F484
LVDS 2Ch
(Right)
■ Output
DDR2
(512Mbitx2)
3D_SYNC
2 LVDS TX (4 channel)
10 bit 1920x1080p@120Hz