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16
15
14
L
K
J
I
H
G
F
E
D
C
B
A
LGE Internal Use Only
16
15
14
13
12
11
10
< 4-1-_PMIC_PM8956_Data >
JTAG_PS_HOLD
MSM_PS_HOLD
D4100
PHONE_ON_N
PMI8952_SYSOK
D4101
VOL_DOWN_PM
PM_PON_RESET_N
+VPWR
VREF_LPDDR3
10/26
C4152
47u
PMIC_SPMI_CLK
PMIC_SPMI_DATA
XO_OUT_A_0
Backup Battery
LNBBCLK_WTR1
BBCLK1_EN
BBCLK1_CXO
SLEEP_CLK
C4106
DNI
+1V8_VREG_L16
PA_THERM_0
R4108
+1V8_VREG_L16
100K
PIN #1,15 must be connected to
main GND using dedicated via
X4100
X1E000361000100
4
3
Thermistor
XTAL2
1
2
XTAL1
GND_thermistor
19.2MHz
C4114
1n
Place caps close to PMIC
C4114 close to X4100 and connect cap GND
through dedicated via to GND plane.
connect to GND_XOADC on Pin #56
Route GND_XOADC as trace to GND plane at one location only.
Do not share GND_XOADC with other gounds.
Do not share GND_XO and GND_RFCLK
with other gounds.
CONNECT GND FROM PIN TO CAPACITOR,
THEN TO SYSTEM GND
< 4-1-17-2_PMIC_PM8956_Power>
Connect GND from PMIC to input capacitor, then to system GND
+VPWR
C4117
+VPWR
C4119
+VPWR
C4121
+VPWR
C4124
+VPWR
C4127
C4128
+1V3_VREG_S3
+1V3_VREG_S3
+1V3_VREG_S3
+2V05_VREG_S4
+VPWR_BOOST_BYPASS
+VPWR_BOOST_BYPASS
+2V05_VREG_S4
C4129
+1V8_VREG_L5
+2V05_VREG_S4
+VPWR
13
12
11
10
9
8
7
135
90
R4102
0
PS_HOLD
SPKR_DRV_P
99
102
KYPD_PWR_N
SPKR_DRV_M
110
R4103
DNI
CBL_PWR_N
107
66
R4104
0
PON_1
MIC1_IN_P/CDC_IN1_P
125
54
RESIN_N
MIC1_IN_M/CDC_IN1_M
78
MIC2_IN
109
92
R4105
0
PON_RESET_N
MIC3_IN
60
80
VPH_PWR
MIC_BIAS1
67
C4116
0.1u
MIC_BIAS2
130
Route codec PDM signals with matching lengths on an inner layer shielded between two GND Layers.
VCOIN
76
Do not add any test point.
EARO_P
68
77
VREF_LPDDR
EARO_M
96
129
OPT_1
PDM_CLK
97
116
OPT_2
PDM_SYNC
47
128
SPMI_CLK
PDM_TX
59
SPMI_DATA
115
PDM_RX0
41
155
RF_CLK1
PDM_RX1
39
142
RF_CLK2
PDM_RX2
42
91
LN_BB_CLK
HPH_REF
44
53
BB_CLK1_EN
HPH_L
U4100
30
65
R4120
0
BB_CLK1
HPH_R
43
PM8956
BB_CLK2
103
HS_DET
98
R4107
0
SLEEP_CLK1
138
R4106
100K
CP_C1_P
104
PA_THERM
93
XO_THERM
56
126
GND_XOADC
CP_C1_M
1
GND_XO_ISO_01
15
114
GND_XO_ISO_02
CP_VNEG
52
VNEG_HPH
2
XTAL_19M_IN
3
XTAL_19M_OUT
23
R4116
0
GPIO_1
36
GPIO_2
16
49
GND_XO
GPIO_3
17
48
GND_RFCLK
GPIO_4
58
GPIO_5
45
85
C4115
0.1u
REF_BYP
GPIO_6
32
134
GND_REF
GPIO_7
120
GPIO_8
127
GND_CP
79
131
GND_CFILT
MPP_01
113
117
GND_SPKR_PA
MPP_02
R4121
0
151
73
GND_BOOST_1
MPP_03
152
86
GND_BOOST_2
MPP_04
R4110
100K
Connect pins #127, 79, 113, 151 and 152 individually to main ground directly.
These are charge pump, speaker, boost GND which are noisy and suould not
be shared with codec GNDs.
38
61
VDD_S1
VREG_S1
62
50
2.2u
GND_S1_01
VSW_S1_01
63
51
L4103
GND_S1_02
VSW_S1_02
74
72
VDD_S2_01
VREG_S2
75
87
2.2u
VDD_S2_02
VSW_S2_01
100
88
L4104
GND_S2_01
VSW_S2_02
101
GND_S2_02
156
143
VDD_S3
VREG_S3
2.2u
145
144
GND_S3_01
VSW_S3_01
158
157
L4105
GND_S3_02
VSW_S3_02
11
37
VDD_S4
VREG_S4
2.2u
13
12
GND_S4_01
VSW_S4_01
25
24
L4106
GND_S4_02
VSW_S4_02
162
123
VDD_S5_01
VREF_NEG_S5
163
124
2.2u
VDD_S5_02
VREG_S5
136
149
GND_S5_01
VSW_S5_01
137
150
GND_S5_02
VSW_S5_02
146
122
VDD_S6_01
U4100
VREF_NEG_S6
159
121
PM8956
2.2u
VDD_S6_02
VREG_S6
148
147
GND_S6_01
VSW_S6_01
161
160
GND_S6_02
VSW_S6_02
105
118
VDD_L1_L19
VREG_L1
132
133
VDD_L2_L23
VREG_L2
111
112
VDD_L3
VREG_L3
9
VREG_L4
21
10
VDD_L4_5_6_7_16
VREG_L5
34
VREG_L6
20
35
VDD_L8_11_12_17_22
VREG_L7
6
33
VDD_L9_10_13_14_15_18_01
VREG_L8
27
18
VDD_L9_10_13_14_15_18_02
VREG_L9
19
VREG_L10
29
VDD_XO_RFCLK
7
VREG_L11
108
57
1u
AVDD_BYP
VREG_L12
28
VREG_L13
141
26
VDD_AUDIO_IO
VREG_L14
40
VREG_L15
64
22
VDD_HPH
VREG_L16
139
31
VDD_CP
VREG_L17
14
VREG_L18
119
VREG_L19
153
4
VSW_BOOST
VREG_L20/XO
140
BOOST_SNS
5
VREG_L21/RFCLK
89
8
VDD_SPKR_PA
VREG_L22
154
106
VREG_BOOST
VREG_L23
C4137
C4149
4.7u
4.7u
R4113
DNI
9
8
7
85
6
5
4
CODEC_MCLK
AOD_RTC
BAT_LOW_ALARM
C4109
BOOST_BYP_BYP
BOOST_BYP_BB
DNI
RGB_EN
WCD_LDO_EN
PM8004_PON_SYNC
VDD_PX_BIAS_MPP_1
NT_READ
VREF_DAC_MPP_3
QUIET_THERM
Even number MPPs can be configured as current sinks,
Odd number MPPs can be configured as analog output voltage buffers
+1V8_VREG_L16
VREG_S1_VSENSE
1u
+0V9_VREG_S1
VDD_MODEM
VREG_S2_VSENSE
1u
+0V9_VREG_S2
VDD_CORE, VDD_CDC_SDC
+1V3_VREG_S3
LDO IN(L1,L2,L3,L19,L23)
2.2u
C4122
22u
C4123
22u
+2V05_VREG_S4
LDO IN(L4,L5,L6,L7,L16,VDD_XO), VDD_HPH, VDD_CP
2.2u
C4125
22u
C4126
22u
VREG_S5_VSENSE_N
VREG_S5_VSENSE_P
L4107
+0V95_VREG_S5
VDD_APCC (LITTLE)
470n
VREG_S6_VSENSE_N
VREG_S6_VSENSE_P
L4108
+0V95_VREG_S6
VDD_MEM
470n
+1V2_VREG_L1
+1V2_VREG_L2
+1V05_VREG_L3
+1V8_VREG_L4
+1V8_VREG_L5
+1V8_VREG_L6
+1V8_VREG_L7
+2V9_VREG_L8
+3V3_VREG_L9
+2V85_VREG_L10
+2V95_VREG_L11
+2V95_VREG_L12
+3V075_VREG_L13
+1V8_VREG_L14_UIM1
+1V8_VREG_L15_UIM2
+1V8_VREG_L16
+2V8_VREG_L17
+2V7_VREG_L18
+1V35_VREG_L19
+2V8_VREG_L22
+1V2_VREG_L23
C4151
C4145
C4138
C4150
C4139
C4140
C4141
C4142
C4143
C4147
C4144
C4153
C4154
4.7u
4.7u
0.1u
0.1u
4.7u
4.7u
1u
1u
4.7u
1u
1u
4.7u
4.7u
6
5
4
3
2
1
L
K
J
I
H
G
F
E
D
MIPI
DDR3
16M DVDD
RF SOCKET(WTR)
Global 1.8V IO, EMMC,NFC_IO
VDD_QFPROM_PRG, Sensor IO
XO IO, USB PHY, PLL2, VDD_A2
C
eMMC
WCN
Sensor VDD
SDC
VDD P2, SDC2
USB_PHY, VDD_MIC_Bias
VDD_P4, VDD_P5, UIM1
VDD_P6, UIM2
XO_Therm, PA_Therm
16M OIS MVDD
RF Front-end(RF Switch)
VDD_A1, VDD_WLAN
B
XO
RF_CLK
16M OIS AVDD
8M W DVDD
LG Electronics
A
TITLE
MODEL NAME
SIZE
DWG NO
REV
A2
PDM NUMBER
Rev
DRAWN BY
SHEET
of
Date
User Name
1
2
Drawing Date
3
2
1
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