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PLDA XpressGX4LP Reference Manual

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XpressGX4LP
Reference Manual
Version 1.0.8 March 2012
Copyright © PLDA 1996-2012

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Summary of Contents for PLDA XpressGX4LP

  • Page 1 XpressGX4LP Reference Manual Version 1.0.8 March 2012 Copyright © PLDA 1996-2012...
  • Page 2 This document is intended only to assist the reader in the use of the product. PLDA shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

  • Page 3: Table Of Contents

    XpressGX4LP Architecture ........
  • Page 4 Appendix A: XpressGX4LP Power Estimation ........
  • Page 5 Table 7: XpressGX4LP clock assignments ........
  • Page 6 Figure 3: XpressGX4LP component side with daughter card ....... . .

  • Page 7: About This Document

    About this Document This document has been written for design managers, system engineers, and designers of ASICs and FPGAs who are evaluating or using the PLDA XpressGX4LP board. Prior knowledge of PCI Express is assumed. Additional Reading PLDA periodically updates its documentation. Please contact PLDA Technical Support or check the Web site at http://www.plda.com for current versions.

  • Page 8: Chapter 1 Introduction

    It is a low-profile, highly-integrated PCI Express FPGA board with dual-10G Ethernet channels engineered for both prototyping and field deployment. The XpressGX4LP board is based on the Altera Stratix IV GX in FBGA 1517 package, and available FPGAs include the EP4SGX230KF40C2N and the EP4SGX530KH40C2N.

  • Page 9: System Requirements

    Introduction System Requirements To use XpressGX4LP board features, you must install the PLDA Software Tools. The PLDA Software Tools can be downloaded from PLDA’s extranet site. You can log in to the extranet from PLDA’s web site www.plda.com. Board Configuration Requirements •...

  • Page 10: Chapter 2 Xpressgx4Lp Architecture

    XpressGX4LP Reference Manual Chapter 2 XpressGX4LP Architecture The XpressGX4LP board is supplied by both the 12V and 3.3V of the PCI Express slot. The PCI Express 12V generates 1.5V, 1.8V, 2.5V, and 0.9V voltages, while the 3.3V generates 1.2V and 3V voltages.

  • Page 11: Block Diagram Of The Board

    XpressGX4LP Reference Manual XpressGX4LP Architecture Block Diagram of the Board The XpressGX4LP board is based on an Altera Stratix IV GX FPGA, as shown below: QDR2 Memories DDR3 Memories XAUI_1 MDIO /2 XAUI_2 Extension Interface Clocks 125 MHz clk_fpga 40 MHz...

  • Page 12: Board Features

    Two boot sectors are available and can be selected with the SW1-4 switch. The XpressGX4LP board can be loaded with either a PCI Express 8x Gen2 Reference Design (in Sector 0) or a dual 10G Ethernet test design (in Sector 1).

  • Page 13: Mechanical Description

    XpressGX4LP Reference Manual XpressGX4LP Architecture Mechanical Description The following diagram illustrates the mechanical architecture of the XpressGX4LP board with the fansink and the supply daughter card mounted. Note: The overall height of the board, that is, the height of the highest component, is 14mm.

  • Page 14: Chapter 3 Xpressgx4Lp Features

    27376kb 1024 Table 2: Stratix IV GX FPGA Resources Board Configuration Module The XpressGX4LP board uses the EPM1270 Max II CPLD as an FPGA Configuration Module for: • FPGA configuration from the Flash Memory (Sector 0 or 1) • Flash updates from PCI Express •...

  • Page 15: Table 3: Transfer Signals Description

    You can use two different methods to program the Flash using the Board Configuration Module. The default method is to use PLDA’s FlashPCI software, which programs the FPGA images into the Flash over PCI Express. This method uses the reference design in order to program the Flash (Sector 0/1). (See the Getting Started for more information about FPGA configuration).

  • Page 16: Table 4: Timing Ranges For Data Transfer

    XpressGX4LP Features XpressGX4LP Reference Manual Signal Name Description cpld_ack Data transfer must be acknowledged by the Flash Access Module; this signal is deasserted when fpga_req is asserted. cpld_busy This signal indicates when the Flash Access Module is busy. Deassertion depends on the specification for Flash memory (typically after 25 to 125ns).

  • Page 17: Table 5: Pin Assignments For The Flash Access Module

    XpressGX4LP Reference Manual XpressGX4LP Features The following table shows pin assignments for the Flash Access Module signals: Signal Signal AC32 fpga_adbus[0] AD30 fpga_adbus[21] AC31 fpga_adbus[1] AB31 fpga_adbus[22] AJ35 fpga_adbus[2] AD28 fpga_adbus[23] AJ34 fpga_adbus[3] AD29 fpga_adbus[24] AH35 fpga_adbus[4] AG31 fpga_adbus[25] AH34...

  • Page 18: Dedicated Clocks

    XpressGX4LP Features XpressGX4LP Reference Manual Dedicated Clocks The following diagram shows clock circuitry for the XpressGX4LP: 40 MHz +/- 100ppm clk_fpga Global Clock (CMOS) AV19 125 MHz +/- 100ppm ext_osc4 n(AE35) Global Clock (LVDS) p(AE34) fpllout1 n(AN1); p(AN2) xpllout1 n(AL1); p(AL2)

  • Page 19: Table 7: Xpressgx4Lp Clock Assignments

    Dual 10G Ethernet PHY xpllout2_p/n G38/G39 LVDS clk_fpga AV19 CMOS Single-ended 40 MHz clock used for the MAX II CPLD and FPGA. Ext_osc4_p/n AF34/AE35 LVDS 125 MHz +/- 100ppm dedicated to PCIe Hard IP. Table 7: XpressGX4LP clock assignments...

  • Page 20: Pci Express Endpoint Connector

    The table below describes pin assignments for the PCI Express Endpoint connector. Shaded signals are defined as optional by the PCI Express Card Electromechanical Specification 2.0, and signals that appear bold are active signals implemented on the XpressGX4LP. Side B...
  • Page 21 XpressGX4LP Reference Manual XpressGX4LP Features Side B Side A PCI Express PCI Express FPGA Pin Signal FPGA Pin Signal connected to mPRSNT2# AT37 mPETn0 mPRSNT#1 AR38 mPERp1 RSVD AR39 mPERn1 AP36 mPETp1 AP37 mPETn1 AJ38 mPERp2 AJ39 mPERn2 AH36 mPETp2...
  • Page 22 XpressGX4LP Features XpressGX4LP Reference Manual Side B Side A PCI Express PCI Express FPGA Pin Signal FPGA Pin Signal connected to mPRSNT#2 mPETn7 mPRSNT#1 Table 8: Pin assignments for the PCI Express endpoint connector...

  • Page 23: Qdrii + Sram

    Note: This feature is only available with the XpressGX4-LP530HE-Gen2 and XpressGX4-LP230HE-Gen2 boards. The XpressGX4LP features four independent banks of QDR2 + SRAM, each capable of addressing up to 9MB in 18-bit wide datapaths. Figure 9: QDRII + SRAM The mounted devices are Cypress CY7C25632KV18-400BZXC. Pin assignments for each bank are shown in the tables below.
  • Page 24 XpressGX4LP Features XpressGX4LP Reference Manual Bank A Bank B FPGA Pin Signal FPGA Pin Signal mem_wps_n[0] mem_wps_n[0] mem_rps_n[0] mem_rps_n[0] mem_doff_n[0] mem_doff_n[0] mem_d[0] mem_d[0] mem_d[1] mem_d[1] mem_d[2] mem_d[2] mem_d[3] mem_d[3] mem_d[4] mem_d[4] mem_d[5] mem_d[5] mem_d[6] mem_d[6] mem_d[7] mem_d[7] mem_d[8] mem_d[8] mem_d[9]...

  • Page 25: Table 10: Qdrii + Sram Banks C + D

    XpressGX4LP Reference Manual XpressGX4LP Features Bank A Bank B FPGA Pin Signal FPGA Pin Signal mem_a[4] mem_a[4] mem_a[5] mem_a[5] mem_a[6] mem_a[6] mem_a[7] mem_a[7] mem_a[8] mem_a[8] mem_a[9] mem_a[9] mem_a[10] mem_a[10] mem_a[11] mem_a[11] mem_a[12] mem_a[12] mem_a[13] mem_a[13] mem_a[14] mem_a[14] mem_a[15] mem_a[15] mem_a[16]...
  • Page 26 XpressGX4LP Features XpressGX4LP Reference Manual Bank C Bank D FPGA Pin Signal FPGA Pin Signal mem_q[8] mem_q[8] mem_q[7] mem_q[7] mem_q[6] mem_q[6] mem_q[5] mem_q[5] mem_q[4] mem_q[4] mem_q[3] mem_q[3] mem_q[2] mem_q[2] mem_q[1] mem_q[1] mem_q[0] mem_q[0] mem_k[0] mem_k[0] mem_k_n[0] mem_k_n[0] mem_cq[0] mem_cq[0] mem_cqn[0]...
  • Page 27 XpressGX4LP Reference Manual XpressGX4LP Features Bank C Bank D FPGA Pin Signal FPGA Pin Signal mem_d[17] mem_d[17] mem_bws_n[0] mem_bws_n[0] mem_bws_n[1] mem_bws_n[1] mem_a[0] mem_a[0] mem_a[1] mem_a[1] mem_a[2] mem_a[2] mem_a[3] mem_a[3] mem_a[4] mem_a[4] mem_a[5] mem_a[5] mem_a[6] mem_a[6] mem_a[7] mem_a[7] mem_a[8] mem_a[8] mem_a[9]...

  • Page 28: Ddr3 Sdram

    Note: This feature is only available with the XpressGX4-LP530HE-Gen2 and XpressGX4-LP230HE-Gen2 boards. The XpressGX4LP features two independent banks of DDR3 SDRAM, each capable of addressing up to 1GB in 16-bit wide data paths: Figure 10: DDR2 SDRAM The mounted devices are Samsung K4B4G0846A-HCH9000 (for 2 x 1GB configuration) or K4B1G0846E-HCH9 (for 2 x 256MB configuration).
  • Page 29 XpressGX4LP Reference Manual XpressGX4LP Features Bank A Bank B FPGA Pin Signal FPGA Pin Signal AP27 mem_dq[12] AM13 mem_dq[12] AP26 mem_dq[13] AP13 mem_dq[13] AU29 mem_dq[14] AL13 mem_dq[14] AN26 mem_dq[15] AP14 mem_dq[15] AT24 mem_ck[0] AU17 mem_ck[0] AU24 mem_ck_n[0] AV17 mem_ck_n[0] AE22...
  • Page 30 XpressGX4LP Features XpressGX4LP Reference Manual Bank A Bank B FPGA Pin Signal FPGA Pin Signal AF25 oct_rup AE14 oct_rup AT25 mem_reset_n AP17 mem_reset_n Table 11: DDR3 SDRAM Banks A + B...

  • Page 31: Ethernet Channels (Sfp+)

    XpressGX4LP Reference Manual XpressGX4LP Features 10G Ethernet Channels (SFP+) The XpressGX4LP features two SFP+ interfaces, providing 10G Ethernet channels that support  10GBase-LRM/SR/LR, 1000Base-X and Passive Direct Attach SFP+ cable. Figure 11: SFP+ interface connectors An APM (AMCC) QT2225-1 XAUI PHY device is used for Ethernet connection. This device supports 10GE and 1GE with an XAUI interface to the FPGA.

  • Page 32: Table 12: Sfp+ Interface Signals

    XpressGX4LP Features XpressGX4LP Reference Manual The following table shows the pin assignments for the SFP+ interfaces: FPGA FPGA Common FPGA SFP+ Link 1 Note Note SFP+ Link 2 Note Signals AM31 eeprom_scl_1 Must be tied AU31 phy_mdc MDIO AT34 eeprom_scl_2 Must be tied to ’Z’.

  • Page 33: Leds

    XpressGX4LP Reference Manual XpressGX4LP Features LEDs Four user-dedicated LEDs are available on the board: Figure 13: LEDs The following table describes pin assignments for the LEDs: FPGA Pin Signal LED Name LED Color user_led0 Green user_led1 Green user_led2 user_led3 Table 13: Pin assignments for the board LEDs...

  • Page 34: 3.10 Mechanical Switches

    3.10 Mechanical Switches Three user switches are available on the solder side of the XpressGX4LP on SW1. These enable 3 IOs to be set to a logical ’0’ or a logical ’1’. A fourth switch (SW1-4) enables you to select the configuration bit stream to load on the FPGA during configuration.

  • Page 35: 3.11 Extension Interface

    XpressGX4LP Reference Manual XpressGX4LP Features 3.11 Extension Interface The Extension Interface includes a UART (RS232/RS485) and a PPS interface (as well as a GND and 2.5V) via a HE10 connector. This connector can optionally be connected to a craft TB5M connector mounted on the board bracket.

  • Page 36: 3.11.1 Uart Interface

    XpressGX4LP Features XpressGX4LP Reference Manual 3.11.1 UART Interface The UART RS232/RS485 interface is managed by a MAX3160 transceiver, as shown below: Rs232_rx1 R1IN Rs232_rx2 R2IN Rs232_tx1 R1OUT Rs232_tx2 R2OUT Rs232_SHDN Rs232_fast Rs232_rs485 Rs232_hdplx Figure 18: UART interface The table below describes pin assignments for the PPS interface:...

  • Page 37: 3.12 Power Supply

    XpressGX4LP Features 3.12 Power Supply The XpressGX4LP board is supplied by both the 12V and 3.3V of the PCI Express slot. These voltages are available on the mezzanine power supply daughter card, which is mounted on the XpressGX4LP by default. The...
  • Page 38 XpressGX4LP Reference Manual Appendix A: XpressGX4LP Power Estimation The following table shows power estimations for the various different configurations of the XpressGX4LP board. (See Appendix C: XpressGX4LP Configuration References for a description of the features of each configuration.) Note: The following figures are provided for illustrative purposes only.
  • Page 39 Appendix B: Voltage and Temperature Absolutes The following table shows the absolute ranges (minimum and maximum) for the board voltages and for operating and storage temperatures. Failure to respect these limitations may result in damage to the XpressGX4LP board. Table 19: Voltage and temperature absolutes Absolute Min.
  • Page 40 XpressGX4LP Reference Manual Appendix C: XpressGX4LP Configuration References The following table shows the various possible configurations of the XpressGX4LP and the features available with each one: Table 20: References and Configurations Board Reference DDR3 SDRAM QDRII + SRAM Ethernet XpressGX4-LP530HE-GEN2...

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