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PLDA XpressGX5LP-SE Reference Manual

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XpressGX5LP-SE
Reference Manual
Version 1.0.0 November 2013
Copyright © PLDA 1996-2013

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Summary of Contents for PLDA XpressGX5LP-SE

  • Page 1 XpressGX5LP-SE Reference Manual Version 1.0.0 November 2013 Copyright © PLDA 1996-2013...
  • Page 2 This document is intended only to assist the reader in the use of the product. PLDA shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

  • Page 3: Table Of Contents

    XpressGX5LP-SE Architecture ........9...
  • Page 4 Table 6: XpressGX5LP-SE clock assignments ........
  • Page 5 Figure 2: XpressGX5LP-SE block diagram ..........10 Figure 3: XpressGX5LP-SE component side with daughter card ......12 Figure 4: JTAG Connector.

  • Page 6: About This Document

    About this Document This document has been written for design managers, system engineers, and designers of ASICs and FPGAs who are evaluating or using the PLDA XpressGX5LP-SE board. Prior knowledge of PCI Express is assumed. Additional Reading PLDA periodically updates its documentation. Please contact PLDA Technical Support or check the Web site at http://www.plda.com for current versions.

  • Page 7: Chapter 1 Introduction

    Chapter 1 Introduction Purpose of the Board The XpressGX5LP-SE board is designed to enable all engineers, even those with little PCI Express experience, to design complex applications using PCIe and 10 Gigabit Ethernet as their main communication interfaces. XpressGX5LP-SE is a low-profile, highly-integrated PCI Express FPGA board with two fully independent 10 G Ethernet channels engineered for both prototyping and field deployment.

  • Page 8: System Requirements

    System Requirements To use XpressGX5LP-SE board features, you must install the PLDA Software Tools. The PLDA Software Tools can be downloaded from PLDA’s extranet site. You can log in to the extranet from PLDA’s web site www.plda.com. Board Configuration Requirements •...

  • Page 9: Chapter 2 Xpressgx5Lp-Se Architecture

    Chapter 2 XpressGX5LP-SE Architecture The XpressGX5LP-SE board is supplied by both the 12 V and 3.3 V of the PCI Express slot. The PCI Express 12 V generates 1.35 V, 1.8 V, 2.5 V, and 0.9 V voltages, while the 3.3 V generates 3.0 V voltages.

  • Page 10: Block Diagram Of The Board

    Ch.2 XpressGX5LP-SE Architecture XpressGX5LP-SE Reference Manual Block Diagram of the Board The XpressGX5LP-SE board is based on an Altera Stratix V GX FPGA, as shown below: Figure 2: XpressGX5LP-SE block diagram...

  • Page 11: Board Features

    FPGA and the CPLD pins. JTAG connector A mini JTAG connector is available on the board. You must use the extender provided by PLDA to configure the FPGA via JTAG, using an Altera USB-Blaster and Quartus. Max V Board Manager The on board MAX V CPLD manages FPGA configuration, as well as IP protection, CvP, partial reconfiguration and power/temperature management.

  • Page 12: Mechanical Description

    Ch.2 XpressGX5LP-SE Architecture XpressGX5LP-SE Reference Manual Mechanical Description The following diagram illustrates the mechanical architecture of the XpressGX5LP-SE board without the fansink mounted. Note: The overall height of the board, that is, the height of the highest component, is 14mm.

  • Page 13: Chapter 3 Xpressgx5Lp-Se Features

    Board Configuration Module 3.2.1 JTAG The XpressGX5LP-SE features a mini JTAG connector. A 10cm cable is provided with the board so you can configure the FPGA with your USB-BLASTER and Quartus. The cable must be plugged into the board as shown in the following picture: Figure 4: JTAG Connector 3.2.2 FlashPROM Configuration...

  • Page 14: Figure 5: Board Configuration Components

    Ch.3 XpressGX5LP-SE Features XpressGX5LP-SE Reference Manual The following figure shows the configuration components of the XpressGX5LP-SE: Boot sector selection switch (SW1-4) LEDs JTAG Conf RST Figure 5: Board configuration components The following diagram shows the board configuration module: Figure 6: Max V 5M2210ZF256 board configuration and management module...

  • Page 15: Table 3: Flashprom Pin Assignments

    XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features The following table shows pin assignments for the FlashPROM: Flash Flash Flash Data FPGA CPLD FPGA CPLD Control FPGA CPLD Address Signal flash_data00 AP33 flash_ad00 AJ29 flash1_adv# AK26 flash_data01 AT33 flash_ad01 AK30 flash1_ce# AL26...

  • Page 16: Table 4: Fpga And Cpld Pin Assignments

    Ch.3 XpressGX5LP-SE Features XpressGX5LP-SE Reference Manual The following table shows the pin assignments for the FPGA and CPLD configuration signals: FPGA Configuration Signals Signal CPLD Signal Name/Function FPGA nConfig nConfig AK35 Conf_done Conf_done Nstatus nstatus Init_done Init_done AL34 Dclk_cpld Dclk_CPLD...
  • Page 17 XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features FPGA Configuration Signals Signal CPLD Signal Name/Function FPGA por_VCCR_GXB VCCR_GXB Power on Reset fpga_power_good FPGA power good AC25 Protocore Dedicated Signals prot0_out prot0_out AG26 prot1_in0 prot1_in0 AE25 prot1_in1 prot1_in1 AF23 prot1_out prot1_out AE24 prot2_in0...

  • Page 18: Table 5: Flash Memory Mapping

    Ch.3 XpressGX5LP-SE Features XpressGX5LP-SE Reference Manual FPGA Configuration Signals Signal CPLD Signal Name/Function FPGA CvP / PR signals (Configuration via protocol / Partial reconfiguration Cvp_confdone Cvp_confdone AT29 pr_done pr_done AT30 pr_error pr_error AU29 pr_ready pr_ready AN29 pr_request pr_request AN30 Table 4: FPGA and CPLD pin assignments...

  • Page 19: Dedicated Clocks

    AV7/AW7 LVDS 200 MHz CLK dedicated to DDR3L Bank0 Osc8 p/n J23/J24 LVDS 200 MHz CLK dedicated to QDR2 banks Gxb Transceiver Clock inputs Pcie_clk_100MHz p/n AF34/AF35 HCSL 100 MHz Transceiver RefCLK for PCIe Gen2 Table 6: XpressGX5LP-SE clock assignments...

  • Page 20: Pci Express Endpoint Connector

    The table below describes pin assignments for the PCI Express Endpoint connector. Shaded signals are defined as optional by the PCI Express Card Electromechanical Specification 2.0, and signals that appear bold are active signals implemented on the XpressGX5LP-SE. Side B...
  • Page 21 XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features Side B Side A PCI Express PCI Express FPGA Pin Signal FPGA Pin Signal AU36 mPETp0 connected to mPRSNT2# AU37 mPETn0 mPRSNT#1 AT38 mPERp1 RSVD AT39 mPERn1 AR36 mPETp1 AR37 mPETn1 AP38 mPERp2 AP39...

  • Page 22: Qdr2+ Sram

    Table 7: Pin assignments for the PCI Express endpoint connector QDR2+ SRAM The XpressGX5LP-SE features two independent banks of QDR2+ SRAM, each capable of addressing up to 144Mbit in an 18-bit wide datapath. The two mounted devices are GSI G581302DT20GE-450..
  • Page 23 XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features Bank 0 Bank 1 FPGA Pin Signal FPGA Pin Signal QDR2a_a10 QDR2b_a10 QDR2a_a11 QDR2b_a11 QDR2a_a12 QDR2b_a12 QDR2a_a13 QDR2b_a13 QDR2a_a14 QDR2b_a14 QDR2a_a15 QDR2b_a15 QDR2a_a16 QDR2b_a16 QDR2a_a17 QDR2b_a17 QDR2a_a18 QDR2b_a18 QDR2a_a19 QDR2b_a19 QDR2a_a20 QDR2b_a20 QDR2a_a21 QDR2b_a21...
  • Page 24 Ch.3 XpressGX5LP-SE Features XpressGX5LP-SE Reference Manual Bank 0 Bank 1 FPGA Pin Signal FPGA Pin Signal QDR2a_d15 QDR2b_d15 QDR2a_d16 QDR2b_d16 QDR2a_d17 QDR2b_d17 QDR2a_Doff QDR2b_Doff QDR2a_q00 QDR2b_q00 QDR2a_q01 QDR2b_q01 QDR2a_q02 QDR2b_q02 QDR2a_q03 QDR2b_q03 QDR2a_q04 QDR2b_q04 QDR2a_q05 QDR2b_q05 QDR2a_q06 QDR2b_q06 QDR2a_q07 QDR2b_q07...

  • Page 25: Ddr3L Sdram

    XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features DDR3L SDRAM The XpressGX5LP-SE features 2 independent banks of DDR3L SDRAM, each capable of addressing 4 GB in a 72-bit wide datapath. The 18 mounted devices are Micron MT41K512M8RA-125. Figure 9: DDR3L SDRAM The following table shows pin assignments for the DDR3L SDRAM:...
  • Page 26 Ch.3 XpressGX5LP-SE Features XpressGX5LP-SE Reference Manual Bank 0 Bank 1 FPGA Pin Signal FPGA Pin Signal ddr3_Bank0_ba1 AV19 ddr3_Bank1_ba1 ddr3_Bank0_ba2 AU16 ddr3_Bank1_ba2 ddr3_Bank0_cas# AR17 ddr3_Bank1_cas# ddr3_Bank0_cke0 AW19 ddr3_Bank1_cke0 ddr3_Bank0_cke1 ddr3_Bank1_cke1 ddr3_Bank0_CKn AN18 ddr3_Bank1_CKn ddr3_Bank0_CKp AN19 ddr3_Bank1_CKp ddr3_Bank0_cs0# AN17 ddr3_Bank1_cs0# ddr3_Bank0_cs1#...
  • Page 27 XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features Bank 0 Bank 1 FPGA Pin Signal FPGA Pin Signal ddr3_Bank0_d24 ddr3_Bank1_d24 ddr3_Bank0_d25 AM10 ddr3_Bank1_d25 ddr3_Bank0_d26 ddr3_Bank1_d26 ddr3_Bank0_d27 AL10 ddr3_Bank1_d27 ddr3_Bank0_d28 ddr3_Bank1_d28 ddr3_Bank0_d29 ddr3_Bank1_d29 ddr3_Bank0_d30 AU10 ddr3_Bank1_d30 ddr3_Bank0_d31 ddr3_Bank1_d31 ddr3_Bank0_d32 AA12 ddr3_Bank1_d32 ddr3_Bank0_d33 AD14...
  • Page 28 Ch.3 XpressGX5LP-SE Features XpressGX5LP-SE Reference Manual Bank 0 Bank 1 FPGA Pin Signal FPGA Pin Signal ddr3_Bank0_d58 AG12 ddr3_Bank1_d58 ddr3_Bank0_d59 AD12 ddr3_Bank1_d59 ddr3_Bank0_d60 AF11 ddr3_Bank1_d60 ddr3_Bank0_d61 AE10 ddr3_Bank1_d61 ddr3_Bank0_d62 AL12 ddr3_Bank1_d62 ddr3_Bank0_d63 AE12 ddr3_Bank1_d63 ddr3_Bank0_d64 AV11 ddr3_Bank1_d64 ddr3_Bank0_d65 AR11 ddr3_Bank1_d65...
  • Page 29 XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features Bank 0 Bank 1 FPGA Pin Signal FPGA Pin Signal ddr3_Bank0_ras# AV16 ddr3_Bank1_ras# ddr3_Bank0_rst# AU17 ddr3_Bank1_rst# ddr3_Bank0_tdqs00n AA15 ddr3_Bank1_tdqs00n ddr3_Bank0_tdqs00p AA14 ddr3_Bank1_tdqs00p ddr3_Bank0_tdqs01n AD17 ddr3_Bank1_tdqs01n ddr3_Bank0_tdqs01p AD18 ddr3_Bank1_tdqs01p ddr3_Bank0_tdqs02n ddr3_Bank1_tdqs02n ddr3_Bank0_tdqs02p ddr3_Bank1_tdqs02p ddr3_Bank0_tdqs03n AP10...

  • Page 30: Dual Sfp+ Interface

    SFPX SUPPLY FAULT available in case of overload on transmitters.. Figure 10: QSFP+ interface The XpressGX5LP-SE Dual SFP+ interface uses FPGA GXB transceivers to enable two 1/10 Gbit Ethernet links: Figure 11: 10/1 Gbs links using the Dual SFP+ interface...

  • Page 31: Table 10: Sfp+ Pin Assignments

    XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features The following table shows the QSFP+ pin assignments on the FPGA: SFP1 FPGA Pin SFP2 FPGA Pin sfp0_frxip_n sfp1_frxip_n sfp0_frxip_p sfp1_frxip_p sfp0_ftxout_n sfp1_ftxout_n sfp0_ftxout_p sfp1_ftxout_p sfp0_gpio3_0 AJ21 sfp1_gpio3_0 AG23 sfp0_gpio3_1 AT20 sfp1_gpio3_1 AG25 sfp0_mod_abs...

  • Page 32: Dual Tri-Color Leds

    Ch.3 XpressGX5LP-SE Features XpressGX5LP-SE Reference Manual Dual Tri-Color LEDs The XpressGX5LP-SE features two dual tri-color (Green/Red/Amber) LEDs on each side of the two SFP+ connectors. These LEDs can be used to display SFP+ information, and can also be used for user-defined purposes.

  • Page 33: Leds

    XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features LEDs Eight user LEDs are available on the board: Figure 12: User LEDs The following table describes pin assignments for the LEDs: Signal FPGA Pin LED Name LED Color user_led0 AJ20 Yellow user_led1 AK21...

  • Page 34: 3.10 Local Reset

    3.11 Mechanical Switches Three user switches are available on the solder side of the XpressGX5LP-SE on SW1. These enable three IOs to be set to a logical ’0’ or a logical ’1’. A fourth switch (SW1-4) enables you to select the configuration bit stream to load on the FPGA during configuration.

  • Page 35: 3.12 Eeproms

    XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features Signal Name FPGA Pin or Function Module user_sw_c SW1-3 max_sw0 Configuration boot selection/ SW1-4 config MAX pin_A10 Table 14: Pin assignments for the mechanical switches 3.12 EEPROMs Two 256k-bit Serial FlashPROMs (M24256BSMN6T) are available on the solder side of the XpressGX5LP for data storage via two I²C links.

  • Page 36: 3.13 Power Supply

    3.13 Power Supply The XpressGX5LP-SE board is supplied by both the 12 V and 3.3 V of the PCI Express slot. These voltages are available on the mezzanine power supply daughter card, which is mounted on the XpressGX5LP-SE by default.

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