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Qorvo PAC25140 User Manual

Pac battery management system
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Power Application Controller Battery Management
PRODUCT USER GUIDE
PAC25140 User Guide Preview
PAC Battery Management System
TM
Multi-Mode Power Manager
Configurable Analog Front End
TM
Application Specific Power Drivers
TM
Arm
®
Cortex
®
-M4F Controller Core
1 of 77

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Summary of Contents for Qorvo PAC25140

  • Page 1 Power Application Controller Battery Management PRODUCT USER GUIDE PAC25140 User Guide Preview PAC Battery Management System Multi-Mode Power Manager Configurable Analog Front End Application Specific Power Drivers ® Cortex ® -M4F Controller Core 1 of 77...

  • Page 2: Table Of Contents

    CONFIGURABLE ANALOG FRONT-END .................31 Overview ........................31 Features ........................31 System Block Diagram ....................32 No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
  • Page 3 9.2.2 Features ......................74 MCU MEMORY MAP ....................76 10 LEGAL INFORMATION .....................77 No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
  • Page 4 Figure 9-1 Top Level Block Diagram ..................73 Figure 9-2 Clock Control Block Diagram ...................75 Figure 9-3 High Level Memory ....................76 No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...
  • Page 5 Table 8-1 Analog Front End Register Map ................41 Table 8-2 ADC MUX channels ....................68 Table 8-3 AFE MUX channels ....................69 No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...
  • Page 6 Register 8-31. SOC.SCPDAC (SCP DAC, SOC 0x28) .............58 Register 8-32. SOC.SCPCFG (SCP Comparator Configuration, SOC 0x29) ......59 Register 8-33. SOC.OCDDAC (OCD DAC, SOC 0x2A) ............59 No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...
  • Page 7 Register 8-48. SOC.WWDTWIN (Windowed Watchdog Timer Window, SOC 0x45) .....64 Register 8-49. SOC.WWDTRST (Windowed Watchdog Timer Reset, SOC 0x46) ....64 Register 8-50. EMUX Packet Structure ...................70 No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 8: Overview

    PAC25140. For detailed information on the MCU and Digital Peripherals in the PAC25140, see the PAC55XX Family User Guide. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 9: Style And Formatting Conventions

    {Rd, }, Rn, Rm Code examples Code examples use monospaced text. b loopA No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.

  • Page 10: Architectural Block Diagram

    ISNSN CONTROL DTSE 16-bit SD ADC VB20 PX.Y No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 10 of 77...

  • Page 11: Analog Register Access

    USART A is a serial communication peripheral that supports a SPI-like protocol that can be used to communicate to the Analog Peripherals for read and write transactions. The Digital No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.

  • Page 12: Usart Configuration

    Write SSPADAT with the value 28h The timing diagram from a write operation is shown below. Figure 4-2 Analog Peripheral Register Write Timing No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...
  • Page 13 PAC25140 Users Guide Preview No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 13 of 77...

  • Page 14: Read Register Example

    For more information on how to configure the DPM to support the USART A peripheral for communicating with the Analog Registers, see the PAC55XX Family User Guide. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.

  • Page 15: Pac25140 Io

    ADC input. For information on how to configure the IO for each of these situations, see the PAC55XX Family User Guide. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.

  • Page 16: Adc Channels

    Package pin Package pin Package pin Package pin Package pin No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 16 of 77...

  • Page 17: Digital Peripheral Pins

    EMUXD GPIOF6 TCPWM6 TDPWM6 TCPHB USDMOSI CANRXD I2CSCL No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 17 of 77...
  • Page 18 PAC25140 Users Guide Preview For more information on how to configure the DPM for the PAC25140, see the PAC55XX Family User Guide. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 19: Configurable Power Manager

    PAC and associated application circuitry. It incorporates a high-voltage power supply controller that is used to convert power from a DC input source to No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.
  • Page 20 SOC.HIBENTER.WUTIMER from 0d to 7d. Refer to Section 34.1.6 for more information on available wake up timing periods. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.
  • Page 21 If the internal temperature (VPTAT) rises above the Fault threshold, the Charge pump, DC/DC and gate drivers will be disabled. The device will indicate this through a latched register bit. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.
  • Page 22 DC/DC will be re-enabled. The temperature hysteresis level for all three thresholds is 10°C. Figure 6-2 Temperature Protection Block Diagram No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 23: Register Summary

    SOC.WATCHDOG SOC Watchdog configuration register SOC.SYSCONF Power Manager system configuration register No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.

  • Page 24: Register Detail

    1b: VCORE fault 6.5.2 SOC.STATUS Register 6-2 SOC.STATUS (System Status, 01h) No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
  • Page 25 PBSTAT_LATCH 0b: Latched push-button not active 1b: Latched push-button active No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 26: Soc.misc

    MCU is asserted. SMEN 0b: Not enabled 1b: Enabled No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.

  • Page 27: Soc.pwrctl

    011b: 500ms 100b: 1s 101b: 2s 110b: 4s 111b: 8s No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 27 of 77...

  • Page 28: Soc.faultenable

    0b: Masked 1b: Not masked This byte is unlocked for writing when UNLOCK = 1b. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 29: Soc.watchdog

    011b: 500ms 100b: 1s 101b: 2s 110b: 4s 111b: 8s No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 29 of 77...

  • Page 30: Soc.sysconf

    HVBK_FREQ 01b: 100kHz 10b: 200kHz 11b: 400kHz Reserved No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 30 of 77...

  • Page 31: Configurable Analog Front-End

    Analog input/output gain amplifier with ADC Input or signal output selection ▪ 2kHz independent clock source No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 32: System Block Diagram

    PAC25140 Users Guide Preview System Block Diagram Figure 7-1 Configurable Analog Front End System Block Diagram No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 33: Functional Description

    To start a IADC Conversion, the SOC.IADCCTL.ADCSTART bit must be set to 1d. The read only bit SOC.VADCCTL.IADCBUSY bit will set to 1d once the conversion is completed. The 16 No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.

  • Page 34: Over-Current Protection

    Over-Current Charge protection (OCC) is designed to is implemented with the OCC DAC (0.5V Vref) and OCC comparator (0.5V Vref) to compare the DAC setting to the differential amplifier No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.

  • Page 35: Over-Current Discharge Protection

    SOC.SIGFAULT.BATOVFLT bit. An active BATOV Fault can be configured to perform the following: • disable the CHG gate driver via the SOC.PROTEN.BATOVCPPROTEN bit, No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 36: Voltage Sensing

    IADCBUSY signal. The 16 bit Cell Voltage conversion can be obtained by reading the SOC.VADCRESHI and SOC.VADCRESLO registers. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.

  • Page 37: 7.4.11 Afe Mux

    A push-button pass through to the MCU can be enabled so that the MCU can read the state of the digital PB pin directly on the PC1 GPIO. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.

  • Page 38: Figure 7-2 Push Button Block Diagram

    ADC channel and convert the ADC counts to C using the following formula: Figure 7-2 Push Button Block Diagram No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 39: Analog I/O 0 (Aio0)

    PAC25140 Users Guide Preview Analog I/O 0 (AIO0) The PAC25140 has an AIO0 module and pin that includes a gain amplifier for analog I/O. The AIO0 pin can be configured as an input to the amplifier with the output of the gain amplifier, AIO0A, routed to the AFE Mux for input to the MCU ADC.

  • Page 40: Miscellaneous

    The user may read or write this register at SOC.GP. This register is only reset on a power-on-reset (POR) or a Push Button (PB) reset. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 41: Afe Registers

    Current ADC Result Hi Byte Current ADC Result Low 0x27 IADCRESLO Byte No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
  • Page 42 WWDTWIN Window Windowed Watchdog Timer 0x46 WWDTRST Reset No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 42 of 77...
  • Page 43 1: 100kHz 2: 200kHz 3: 400KHz VP_PD_DIS VP Pull Down Disable No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
  • Page 44 . SOC.AFEMUXSEL (AFE Mux Select, SOC 0x04) NAME ACCESS RESET DESCRIPTION Reserved No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 44 of 77...
  • Page 45 EMUX_EN=0, but is readable by the SOC Bridge SPI I/F at anytime. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
  • Page 46 Note: If all wake-up enables are set to Disabled when HIBENTER.HIB is written, then PBWAKEN and PACKWAKEN will be set to 1 as a fail safe to allow the device to be brought out of hibernate. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.
  • Page 47 Following a Fault Reset, read the PWRFAULT and TEMPFAULT registers to determine which faults caused the reset. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...
  • Page 48 Push Button Enabled PBEN 0: Disabled 1: Enabled No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 48 of 77...
  • Page 49 KEY field is self clearing to 0x0 after any write to one of the select registers. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...
  • Page 50 DSG FET will be disabled BATOVCPROTEN Battery Over Voltage No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
  • Page 51 FUSEEN gate drive output Note: This register requires a write of PROT_KEY before register can be written. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...
  • Page 52 HVCP Fault Interrupt HVCPFLTEN Enable Note: This register requires a write of PROT_KEY before register can be written. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...
  • Page 53 RESET DESCRIPTION Reserved EMUX Fault Interrupt EMUXFLTEN Enable No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 53 of 77...
  • Page 54 BATOVFLTEN Fault Interrupt Enable Note: This register requires a write of PROT_KEY before register can be written. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...
  • Page 55 OCDFLT Discharge Fault Flag Battery Over Voltage BATOVFLT Fault Flag No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 55 of 77...
  • Page 56 BATOV comparator. Note: This register requires a write of PROT_KEY before register can be written. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...
  • Page 57 ACCESS RESET DESCRIPTION Voltage ADC Result VADCRES[15:8] MSByte No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 57 of 77...
  • Page 58 ACCESS RESET DESCRIPTION SCPDAC SCP DAC Setting – No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 58 of 77...
  • Page 59 OCD comparator. Note: This register requires a write of PROT_KEY before register can be written. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...
  • Page 60 Example: TIMEBASE = 1, BLANKSF = 2; So, Blanking Time = 2uS * 3 = 6uS OCC Comparator Hysteresis is fixed at 25mV No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.
  • Page 61 Cell 19 Enable CEN18 Cell 18 Enable CEN17 Cell 17 Enable No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
  • Page 62 . SOC.GP (General-Purpose Register, SOC 0x40) NAME ACCESS RESET DESCRIPTION General-purpose read-write register. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 62 of 77...
  • Page 63 Note: The WWDT runs off of a 32kHz clock that is independent of the 4MHz CLKREF that the MCU runs off. When the WWDT is used, it can help meet Class B Safety requirements. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.
  • Page 64 - This register shall automatically be cleared to 0x00, and shall always read 0x00. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.

  • Page 65: Driver Manager

    Cell Balancing The PAC25140 contains integrated cell balancing FETs for up to 20 cells. Features No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 66: Block Diagram

    VADCCTL.VBMUXSEL VADCRESHI.VADCRES VB14_SCL VADCRESLO.VADCRES VB14 CFGCB1.VB2 VB1_SCL CFGCB1.VB1 No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 66 of 77...
  • Page 67 To start the cell balancing process, simply set the respective VBx cell balancing enable bit. This can be accomplished by writing to the SOC.CFGCB1, SOC.CFGCB2 and SOC.CFGCB3 registers. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.

  • Page 68: Afe Mux And Emux

    The AFE MUX channel may be selected from the EMUX data sent from the ADC sequencer. The channels available on the AFE MUX are shown in the table below. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.

  • Page 69: Emux

    The format of the EMUX command used to control the AFE MUX is shown below. The EMUX data is transmitted MSb first. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.
  • Page 70 18 = BATOVDAC 19 = VIN / 50 20 = PACK+ / 50 21 = VCP / 50 No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 71: Figure 9-1 Emux Timing Diagram

    EMUX clock falling edge, the AFE will read the AFEMUXSEL[4:0] data. At this time the AFE will set the AFE MUX to the proper channel, according to this data. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev.

  • Page 72: Arm ® Cortex M4F Reference

    The Arm® Cortex®-M4 Devices Generic User Guide contains documentation for the Arm® Cortex®-M4F’s Embedded Trace MacrocellTM No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 73: Pac25Xxx Architecture

    DATA ACQUISITION AND SEQUENCER PX.Y 12-BIT DTSE SYSTEM CONTROL No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 73 of 77...

  • Page 74: System And Clock Control (Scc)

    8 levels of priority Note that only some devices contain the pins for the crystal input and output. No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 ©...

  • Page 75: Figure 9-2 Clock Control Block Diagram

    PAC25140 Users Guide Preview Figure 9-2 Clock Control Block Diagram No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc. 75 of 77...

  • Page 76: Mcu Memory Map

    PAC25140 Users Guide Preview MCU MEMORY MAP Figure 9-3 High Level Memory No portion of this document may be reproduced or reused in any form without Qorvo’s prior written consent www.qorvo.com Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.

  • Page 77: 10 Legal Information

    Users Guide Information is suitable for use in a particular application. © 2023 Qorvo US, Inc. All rights reserved. This document is subject to copyright laws in various jurisdictions worldwide and may not be reproduced or distributed, in whole or in part, without the express written consent of Qorvo US, Inc.

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