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JVC DR-MH20SUC Service Manual page 26

Dvd&hdd video recorder
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Block diagrams
DIGITAL 0 2
PHY_RESET[L]
5
PHY_LREQ PHY_CLK
PHY_CNA PHY_CTL[0],[1]
PHY_DATA[0-7] PHY_LPS
PHY_LINK_ON
SDRAM_DQ16 to 31
SDRAM_DQ0 to 15
4
SDRAM_A0 to 15
SDRAM_DQM0 to 3
SDRAM_DQS0 to 3
3
SDRAM_CKE
SDRAM_RAS_L
SDRAM_CAS_L
SDRAM_WE_L
SDRAM_CLK0,1
SDRAM_CLK_L0,1
2
1
Media processor section (SHEET 4)
A
2-5
IEEE1394
Controller
IC1801
IEEE1394 Section (SHEET 2)
RA1613 to
DDR_DQ16 to 31
RA1616
DDR_DQ0 to 15
RA1609 to
RA1612
DDR_CS0
RA1642
DDR_CS1
RA1641
RA1625 to
DDR_BA1,2
RA1628
DDR_A0 to 12
DDR_DQM0 to 3
RA1601 to
DDR_DQS0 to 3
RA1604
DDR_RAS_L DDR_CKE
DDR_CAS_L DDR_WE_L
RA1653 to
RA1660
DDR_CLK0,1
DDR_CLK_L0,1
RA1613 to
RA1616
ATA2_DMAACK[L] ATA2_INTRQ ATA2_ADD0 to 4
ATA2_DIOR[L] ATA2_DIOW[L] ATA2_IORDY
ATA2_DAT0 to 15 ATA2_RESET ATA2_DMARQ
Media
ATA_DMAACK[L] ATA_INTRQ ATA_ADD0 to 4
ATA_DIOR[L] ATA_DIOW[L] ATA_IORDY
processor
ATA_DAT0 to 15 ATA_RESET ATA_DMARQ
IC1401
SYS_RESET[L] VIDEO_RXD
K_BUS_CLK K_BUS_REQ K_BUS_IN/OUT
IC1404
IC1405
VIDEO_RST[L] SPI_MOSI SPI_CLK VIDEO_CS
RD/WR[L] ALE OE[L]/LDS[L] MADD1 to 22 CS[0] E5_RESET[L]
B
TPA+ TPA- TPB+ TPB-
DDR SDRAM
DDR SDRAM
IC1601
IC1602
DDR SDRAM Section (SHEET 3)
C
J4112
IEEE1394
Terminal
DDR SDRAM
DDR SDRAM
IC1603
IC1604
D

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