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P100 1
SMW200-22 C
L1003
1
2
MLB-201209-0120P-N 2
P_+16 V
C106 3
C106 1
C107 2
0.1uF
47u F
0.1uF
3
4
50 V
25 V
READY
50 V
5
6
L1016
MLB-201209-0120P-N 2
P_+12 V
C106 4
C106 6
C106 7
P_+5 V
7
8
0.1uF
100 uF
0.1uF
16 V
16 V
16 V
READY
C107 3
220u F
L1017
9
10
16 V
MLB-201209-0120P-N 2
4.7K
R812 3
C107 0
C101 3
C106 2
L1018
0.1uF
4.7uF
0.1uF
11
12
MLB-201209-0120P-N 2
16 V
10 V
16 V
READY
P_+5V_COR E
READY
C107 1
C101 0
4.7uF
C106 5
C106 0
R103 9
13
14
0.1uF
10 V
220u F
0.1uF
0
16 V
16 V
16 V
ERROR_OU T
5V_MNT
READY
READY
15
16
C106 8
C101 9
0.1uF
0.1uF
16 V
16 V
READ Y
17
18
R104 1
0
READ Y
AC_DE T
C101 8
C107 4
10pF
R103 8
19
20
0.1uF
R104 0
0
16 V
0
50V
RL_ON/PWR_ONOF F
V A VS_ON
C100 7
READ Y
READ Y
C102 7
R103 7
21
22
C100 8
C102 8
4 . 7 uF
10pF
M5V_ON
0
4 . 7 uF
10pF
6.3V
50V
6.3V
50V
C101 2
47uF
C106 9
16V
0.1uF
S t a n d b y Vo l t a g e
P_+5 V
IC100 3
AZ1117H-3.3
INPUT
3
1
ADJ/GND
2
C100 3
OUTPU T
0.1uF
L1007
16 V
MLB-201209-0120P-N 2
+3.3V_S TBY
C100 6
C101 4
C190 8
10u F
0.1uF
0 . 1 uF
16 V
16V
6.3V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATE S
SPECIAL FEATURES IMPORTANT FOR PRO TECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC .
Copyright©2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
P_+5V_COR E
BA18DD0 WHFP
1.8V_DOUGLAS_E N
CTL
1
VCC
2
12V Li ne
C100 5
0.1uF
16 V
P_+12 V
+8V_MS P
IC1005
IC101 1
KIA7808AF
KIA7805AF
I
1
3
O
I
1
3
O
+5V_TUNE R
C108 9
2
2
0.1uF
C103 0
C103 7
C101 7
16 V
C
0.1uF
C
0.1uF
4.7uF
C104 1
16 V
10 V
100u F
16 V
READY
16V
C100 4
0.22u F
16 V
P_+5V_COR E
O ver cu r r en t p r ot e c t io n c an be o per a t ed
IC100 2
P_+5 V
MP2305D S
D100 1
KDS22 6
C109 1
0.1uF
A
AC
BS
1
8
SS
50 V
C
L1004
1uF
MLB-201209-0120P-N 2
I N
EN
2
7
C109 2
+5 V
C109 0
C109 3
C109 4
S W
COM P
0.1uF
4.7uF
100u F
3
6
16 V
10 V
16 V
C100 2
READY
4.7uF
R101 4
47 K
10 V
GN D
FB
4
5
R101 6
47 K
C
R101 5
B
4.7K
2SC305 2
RL_ON/PWR_ONOF F
Q100 4
E
1.26V_DOUGLAS_E N
1 . 8 V R eg ul a to r f or TU N ER
6
L o c a t e c l o s e t o t h e T U N E
R
IC100 1
P_+5V_COR E
KIA78R33 F
1
2
3
4
5
S t a n d b y Vo l t a g e
R103 3
6
0
IC101 2
L1012
KIA78R33 F
MLB-201209-0120P-N 2
1
2
3
4
5
P_+5 V
C108 1
C108 2
100u F
0.1uF
16 V
16 V
R102 3
C109 6
C108 3
0
C108 4
0 . 1 uF
0.1uF
10u F
16V
16 V
6.3V
R102 2
C102 9
0
3.3V_O N
0.1uF
+3.3V_TUNE R
16 V
C105 1
0.1uF
C100 9
16 V
10u F
6.3V
3.3V_O N
L1014
MLB-201209-0120P-N 2
+3.3V
IC100 4
C105 8
C105 7
0.1uF
100u F
AZ1117H-1.8TRE1(EH13A )
16 V
16 V
INPUT
3
1
ADJ/GND
2
OUTPU T
+1.8V
C109 5
C102 1
C102 2
0 . 1 uF
0.1uF
16V
100u F
16 V
16 V
C101 6
10u F
6.3V
READY
IC100
FLI10610H-AA
C2
A1P
LVTX_ODD_CH0N_DISP2 3
R50 4
22
C50 2
0.1uF
E2
COMP2_ Y
A2P
LVTX_ODD_CH0P_DISP2 2
R50 5
22
C50 3
0.1uF
G2
COMP1_ Y
A3P
LVTX_ODD_CH1N_DISP2 1
R51 3
22
C51 1
0.1uF
J2
VGA_B
A4P
For CHAPLIN
B_GR A
LVTX_ODD_CH1P_DISP2 0
R50 7
56
C50 5
0.1uF
D2
For DOUGLAS
AN
LVTX_ODD_CH2N_DISP1 9
LVTX_ODD_CH2P_DISP1 8
B1
B1P
LVTX_ODD_CLKN_DISP1 7
R509
C50 7
0.1uF
D1
22
COMP2_P b
B2P
LVTX_ODD_CLKP_DISP1 6
R51 0
22
C50 8
0.1uF
G1
COMP1_P b
B3P
LVTX_ODD_CH3N_DISP1 5
J1
R50 8
22
C50 6
0.1uF
B4P
For CHAPLIN
VGA_G
G_GR A
LVTX_ODD_CH3P_DISP1 4
F2
For DOUGLAS
R51 2
56
C51 0
0.1uF
BN
LVTX_ODD_CH4N_DISP 3
LVTX_ODD_CH4P_DISP 2
C1
C1P
LVTX_ODD_CH5N_DISPC LK
E1
R51 4
22
C51 2
0.1uF
COMP2_P r
C2P
LVTX_ODD_CH5P_DISPD E
R515
C513
0 . 1 uF
H1
22
COMP1_P r
C3P
K1
R50 3
22
C50 1
0.1uF
C4 P
VGA_R
R_GR A
For CHAPLIN
LVTX_EVN_CH0N_DISP1 3
H2
For DOUGLAS
R51 7
56
C51 5
0.1uF
CN
LVTX_EVN_CH0P_DISP1 2
LVTX_EVN_CH1N_DISP1 1
D3
SV1P
LVTX_EVN_CH1P_DISP1 0
R51 9
22
C51 7
0.1uF
F3
SIDE_YIN/SIDE_VI N
SV2P
LVTX_EVN_CH2N_DISP 9
R52 0
22
C51 8
0.1uF
H3
TU_MAIN
SV3P
LVTX_EVN_CH2P_DISP 8
J3
SV4P
LVTX_EVN_CLKN_DISP7
R52 2
56
C52 0
0.1uF
K2
SVN
LVTX_EVN_CLKP_DISP 6
LVTX_EVN_CH3N_DISP 5
J6
H_SYNC_P C
AHS_AC S
LVTX_EVN_CH3P_DISP 4
H6
V_SYNC_P C
AV S
LVTX_EVN_CH4N_DISP 1
LVTX_EVN_CH4P_DISP 0
J4
VOUT2
LVTX_EVN_CH5N_DISPV S
LVTX_EVN_CH5P_DISPH S
G6
SCAR T_F B
A10
TXCLK_SW-
ARXCM
VDAC_COMP
B10
TXCLK_SW+
ARXCP
VDAC_BU_N
A9
TX0_SW -
ARX0M
VDAC_RV_N
B9
TX0_SW +
ARX0P
VDAC_GY_YC_ N
A8
TX1_SW -
ARX1M
VDAC_RS ET
B8
TX1_SW +
ARX1P
A7
TX2_SW -
ARX2M
VDAC_BU_P_ 1
B7
TX2_SW +
ARX2P
VDAC_BU_P_ 2
VDAC_GY_YC_ P
B11
HP_D ET_S /W_3
HDMI_A_HPD
C11
HP_D ET_S /W_1
HDMI_B_HP D
A11
HDMI_CEC
A6
BRXCM
TXCLK_BUF-
B6
TXCLK_BUF+
BRXCP
A5
TX0_BUF -
BRX0M
B5
TX0_BUF +
BRX0P
A4
TX1_BUF -
BRX1M
B4
TX1_BUF +
BRX1P
A3
TX2_BUF -
BRX2M
B3
TX2_BUF +
BRX2P
+3.3V_HDMI_DOUGLA S
R52 3
R52 6
D9
1
REXT
249
1%
+5 V
IC502
NLASB3157DFT2 G
B1
SELEC T
1
6
DTV/MNT_SWITCH
+5 V
GND
VCC
2
5
C55 0
B0
A
0.1uF
3
4
50 V
DTV/MNT_VOUT
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATE S
SPECIAL FEATURES IMPORTANT FOR PRO TECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC .
IC100
FLI10610H-AA
CPL_DDR2_D[0 ]
F24
P27
CPL_DDR2_D[1 ]
M24
DDR_D 0
DDR_A0
U29
CPL_DDR2_D[2 ]
DDR_D 1
DDR_A1
J 25
R26
CPL_DDR2_D[3 ]
K26
DDR_D 2
DDR_A2
U26
CPL_DDR2_D[4 ]
DDR_D 3
DDR_A3
M26
P25
CPL_DDR2_D[5 ]
E25
DDR_D 4
DDR_A4
T28
CPL_DDR2_D[6 ]
DDR_D 5
DDR_A5
L25
R27
CPL_DDR2_D[7 ]
F26
DDR_D 6
DDR_A6
V28
DDR_D 7
DDR_A7
CPL_DDR2_D[8 ]
E29
R29
CPL_DDR2_D[9 ]
L29
DDR_D 8
DDR_A8
T29
DDR_D 9
DDR_A9
CPL_DDR2_D[10]
H28
V25
CPL_DDR2_D[11]
J 29
DDR_D1 0
DDR_A1 0
R28
CPL_DDR2_D[0-31 ]
DDR_D1 1
DDR_A1 1
CPL_DDR2_D[12]
L27
V26
CPL_DDR2_D[13]
DDR_D1 2
DDR_A1 2
E27
DDR_D1 3
CPL_DDR2_D[14]
K28
CPL_DDR2_D[15]
DDR_D1 4
F28
DDR_D1 5
DDR_DM 0
K24
CPL_DDR2_D[16]
Y24
J 27
CPL_DDR2_D[17]
DDR_D1 6
DDR_DM 1
AF28
DDR_D1 7
DDR_DM 2
AD24
CPL_DDR2_D[18]
AC25
AC27
CPL_DDR2_D[19]
DDR_D1 8
DDR_DM 3
AD26
CPL_DDR2_D[20]
AF26
DDR_D1 9
CPL_DDR2_D[21]
DDR_D2 0
W25
U28
CPL_DDR2_D[22]
AE25
DDR_D2 1
DDR_BA0
T27
CPL_DDR2_D[23]
DDR_D2 2
DDR_BA1
Y26
CPL_DDR2_D[24]
W29
DDR_D2 3
P24
CPL_DDR2_D[25]
DDR_D2 4
DDR_CAS_ N
AE29
N26
CPL_DDR2_D[26]
AB28
DDR_D2 5
DDR_RAS_ N
N25
IC1000
CPL_DDR2_D[27]
DDR_D2 6
DDR_CS_ N
AC29
T25
CPL_DDR2_D[28]
AE27
DDR_D2 7
DDR_WE_ N
CPL_DDR2_D[29]
DDR_D2 8
+1.8V_DOUGLAS_DD R
W27
P29
CPL_DDR2_D[30]
AD28
DDR_D2 9
DDR_C K
N29
NC
DDR_D3 0
DDR_CK_ N
5
CPL_DDR2_D[31]
Y28
DDR_D3 1
U27
DDR_CK E
4
VOUT
CPL_DDR2_DQS0_ P
H25
H26
DDR_DQS 0
M27
CPL_DDR2_DQS0_ N
DDR_DQS0_ N
DDR_OD T
C108 7
C108 0
CPL_DDR2_DQS1_ P
G28
3
0.1uF
10u F
DDR_DQS 1
16 V
6.3V
CPL_DDR2_DQS1_ N
G29
DDR_DQS1_ N
DDR_CA L
U24
CPL_DDR2_DQS2_ P
AB25
GN D
DDR_DQS 2
CPL_DDR2_DQS2_ N
AB26
DDR_DQS2_ N
CPL_DDR2_DQS3_ P
AA28
DDR_DQS 3
CPL_DDR2_DQS3_ N
AA29
DDR_DQS3_ N
C101 1
C102 4
10u F
10u F
L1008
22uH
6.3V
6.3V
READY
+1.26V_DOUGLAS_ D
READ Y
C109 7
C108 8
C102 6
0 . 1 uF
0.1uF
220u F
16V
16 V
16V
DDR2_D[0-31 ]
DDR2_VRE F
IC701
C75 2
10u F
6.3V
HYB18T512160AF-3S
C75 3
0.1uF
16 V
C70 2
0.1uF
VREF
DQ0
DDR2_A[0-12 ]
J2
G8
G2
DQ1
DDR2_A[0 ]
A0
H7
DQ2
C101 5
C102 0
M8
H3
DQ3
560p F
0.015uF
DDR2_A[1 ]
A1
M3
50 V
DDR2_A[2 ]
A2
H1
DQ4
50 V
M7
H9
DQ5
R100 4
DDR2_A[3 ]
A3
N2
DDR2_A[4 ]
A4
F1
DQ6
6.8K
N8
DQ7
DDR2_A[5 ]
A5
N3
F9
DDR2_A[6 ]
A6
C8
DQ8
R100 3
N7
DQ9
1K
DDR2_A[7 ]
A7
P2
C2
DDR2_A[8 ]
A8
D7
DQ10
1%
P8
DQ11
DDR2_A[9 ]
A9
P3
D3
DDR2_A[10 ]
D1
DQ12
A10/AP
M2
DQ13
DDR2_A[11]
A11
P7
D9
DDR2_A[12 ]
B1
DQ14
A12
R2
DQ15
B9
BA0
DDR2_BA 0
L2
BA1
L3
DDR2_BA 1
A1
VDD5
VDD4
R71 1
E1
DDR2_C K
200
C K
J8
J9
VDD3
C K
VDD2
DDR2_CK_ N
K8
M9
DDR2_CK E
CKE
K2
R1
VDD1
DDR2_ODT_ T
OD T
K9
CS
L8
A9
VDDQ10
DDR2_CS_ N
DDR2_RAS_ N
RAS
K7
C1
VDDQ9
CAS
VDDQ8
DDR2_CAS_ N
L7
C3
WE
K3
C7
VDDQ7
DDR2_WE_ N
VDDQ6
C9
+3.3V_DOUGLA S
LDQS
E9
VDDQ5
DDR2_DQS0_ P
F7
VDDQ4
DDR2_DM[0-3 ]
DDR2_DQS1_ P
UDQ S
B7
G1
G3
VDDQ3
VDDQ2
DDR2_DM[0 ]
G7
LDM
F3
G9
VDDQ1
DDR2_DM[1 ]
UDM
B3
DDR2_DQS0_ N
LDQS
VSS 5
E8
A3
DDR2_DQS1_ N
UDQ S
A8
E3
VSS 4
VSS 3
J3
NC4
N1
VSS 2
L1
VSS 1
NC5
R3
P9
NC6
R7
NC1
B2
VSSQ1 0
A2
B8
VSSQ 9
NC2
E2
NC3
A7
VSSQ 8
R8
D2
VSSQ 7
D8
VSSQ 6
VSSQ 5
VSSD L
J7
E7
F2
VSSQ 4
+1.8V_DOUGLAS_DD R
VSSQ 3
F8
H2
VSSQ 2
VDDL
VSSQ 1
J1
H8
C70 1
0.1uF
POWE R
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATE S
SPECIAL FEATURES IMPORTANT FOR PRO TECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC .
PANNEL WAFER
P50 2
P50 1
HD
SMW200-40 C
AH29
RX0-
AJ29
RX0+
AH28
RX1-
AJ28
RX1+
AH27
2
2
1
1
RX2-
AJ27
RX2+
4
4
3
3
AH26
RXCLK-
AJ26
6
6
5
5
RXCLK+
AH25
RX3-
8
8
7
7
AJ25
RX3+
R58 8
AH24
10
10
9
9
100
100
R58 9
RX4-
SDA2_3.3 V
SCL2_3.3 V
AJ24
RX4+
12
12
11
11
AG29
RX0-
RX0+
AG28
14
14
13
13
RX1+
RX1-
16
16
15
15
AH23
RX2-
RX2+
CH0E -
AJ23
18
18
17
17
CH0E +
RXCLK+
RXCLK-
AF23
CH1E -
20
20
19
19
AG23
RX3+
+3.3V
RX3-
CH1E +
AH22
22
22
21
21
CH2E -
RX4+
RX4-
AJ22
CH2E +
24
24
23
23
R53 8
0
AF22
PC_SER_DA T A
CKE-
0
PC_SER_CL K
R53 7
R54 4
0
AG22
MODULE_SER_DA T A
26
26
25
25
CKE+
ROM_D L
MODULE_SER_CL K
0
R54 3
DISP_E N
AH21
ROM_D L
R587
100
R590
CH3E -
28
27
HD
10K
HD
AJ21
CH0E +
R527
0
CH0E -
CH3E +
FHD
AF21
30
29
CH4E -
CH1E +
CH1E -
AG21
CH4E +
32
31
AG25
CH2E +
CH2E -
AG24
34
33
CKE+
CKE-
36
35
CH3E +
CH3E -
38
37
CH4E +
CH4E -
AG5
C52 3
0.1uF
40
39
AH1
DISP_E N
R528
100
AH2
FHD
R529
10K
AH3
FHD
R55 5
AH4
1.8K
1%
AJ1
AJ2
SMW200-26 C
AJ3
R551
R552
75
75
1%
1%
LVDS,AFE
CPL_DDR2_A[0 ]
CPL_DDR2_A[1 ]
CPL_DDR2_A[2 ]
CPL_DDR2_A[3 ]
CPL_DDR2_A[4 ]
CPL_DDR2_A[5 ]
CPL_DDR2_A[0-12 ]
CPL_DDR2_A[6 ]
CPL_DDR2_A[7 ]
CPL_DDR2_A[8 ]
CPL_DDR2_A[9 ]
CPL_DDR2_ A[ 10]
CPL_DDR2_A[11 ]
CPL_DDR2_ A[ 12]
CPL_DDR2_DM[0 ]
CPL_DDR2_DM[1 ]
CPL_DDR2_DM[2 ]
CPL_DDR2_DM[3 ]
CPL_DDR2_DM[0-3 ]
+1.8V_DOUGLAS_DD R
CPL_DDR2_BA 0
CPL_DDR2_BA 1
DDR2_VRE F
CPL_DDR2_CAS_ N
CPL_DDR2_RAS_ N
CPL_DDR2_CS_ N
CPL_DDR2_WE_ N
C755
C754
0 . 1 uF
0 . 1 uF
50V
50V
CPL_DDR2_C K
CPL_DDR2_CK_ N
CPL_DDR2_CK E
DDR2_OD T
R70 9
294
1%
10u F
C75 1
IC703
6.3V
DDR2_VRE F
C75 0
0.1uF
HYB18T512160 AF-3S
16 V
DDR2_D[0 ]
DDR2_A[0-12 ]
C72 2
VREF
DQ0
DDR2_D[16 ]
J2
G8
DDR2_D[1 ]
0.1uF
G2
DQ1
DDR2_D[17 ]
DDR2_D[2 ]
DDR2_D[18 ]
DDR2_A[0 ]
A0
H7
DQ2
DDR2_D[3 ]
M8
H3
DQ3
DDR2_D[19 ]
DDR2_A[1 ]
A1
M3
DDR2_D[20 ]
DDR2_D[4 ]
DDR2_A[2 ]
A2
H1
DQ4
DDR2_D[5 ]
M7
H9
DQ5
DDR2_D[21 ]
DDR2_A[3 ]
A3
N2
DDR2_D[22 ]
DDR2_D[6 ]
DDR2_A[4 ]
A4
F1
DQ6
DDR2_D[7 ]
N8
DQ7
DDR2_D[23 ]
DDR2_A[5 ]
A5
N3
F9
DDR2_D[24 ]
DDR2_D[8 ]
DDR2_A[6 ]
A6
C8
DQ8
DDR2_D[9 ]
N7
DQ9
DDR2_D[25 ]
DDR2_A[7 ]
A7
P2
C2
DDR2_D[26 ]
DDR2_D[10 ]
DDR2_A[8 ]
A8
D7
DQ10
DDR2_D[11 ]
P8
DQ11
DDR2_D[27 ]
DDR2_A[9 ]
A9
P3
D3
DDR2_D[28 ]
DDR2_D[12 ]
DDR2_A[10 ]
D1
DQ12
DDR2_D[13 ]
A10/AP
M2
DQ13
DDR2_D[29 ]
DDR2_A[11]
A11
P7
D9
DDR2_D[14 ]
DDR2_A[12 ]
B1
DQ14
DDR2_D[30 ]
DDR2_D[15 ]
+1.8V_DOUGLAS_DD R
A12
R2
DQ15
DDR2_D[31 ]
B9
+1.8V_DOUGLAS_DD R
DDR2_BA 0
BA0
L2
DDR2_BA 1
BA1
L3
A1
VDD5
VDD4
C74 1
R71 2
200
E1
330u F
DDR2_C K
C K
J8
J9
VDD3
6.3V
C K
VDD2
C72 0
C72 1
DDR2_CK_ N
K8
M9
330u F
1uF
DDR2_CK E
CKE
K2
R1
VDD1
6.3V
6.3V
DDR2_ODT_ T
OD T
K9
CS
L8
A9
VDDQ10
DDR2_CS_ N
DDR2_RAS_ N
RAS
K7
C1
VDDQ9
CAS
VDDQ8
DDR2_CAS_ N
L7
C3
DDR2_WE_ N
WE
K3
C7
VDDQ7
VDDQ6
C9
LDQS
E9
VDDQ5
DDR2_DQS2_ P
F7
VDDQ4
DDR2_DQS3_ P
UDQ S
B7
G1
G3
VDDQ3
VDDQ2
DDR2_DM[2 ]
G7
LDM
F3
G9
VDDQ1
DDR2_DM[3 ]
UDM
B3
DDR2_DQS2_ N
LDQS
VSS 5
E8
A3
DDR2_DQS3_ N
UDQ S
A8
E3
VSS 4
VSS 3
J3
NC4
N1
VSS 2
L1
VSS 1
NC5
R3
P9
NC6
R7
NC1
B2
VSSQ1 0
A2
B8
VSSQ 9
NC2
E2
NC3
A7
VSSQ 8
R8
D2
VSSQ 7
D8
VSSQ 6
VSSQ 5
VSSD L
J7
E7
F2
VSSQ 4
+1.8V_DOUGLAS_DD R
VSSQ 3
F8
H2
VSSQ 2
VDDL
VSSQ 1
J1
H8
C72 3
0.1uF
P80 3
12505WS-12A0 0
L803
I R
HB-1S2012-121J T
1
I R
C827
C81 0
GND
10pF
680pF
2
50V
READ Y
L802
KEY2
3
KEY2
HB-1S2012-121J T
GND
C828
C80 8
10pF
5pF
4
50V
READ Y
READY
KEY1
L805
5
KEY1
C829
HB-1S2012-121J T
C80 9
GND
10pF
5pF
P_+5V
6
50V
READ Y
READY
MLB-201209-0120P-N 2
STBY_5 V
7
C80 3
C80 7
C830
4.7uF
L801
GND
10 V
0.1uF
10pF
8
50 V
50V
L806
READ Y
HB-1S2012-121J T
LED_R
LED_R
9
C831
C832
GND
100p F
470p F
10
50V
50V
LED_G
HB-1S2012-121J T
11
L804
LED_G
C833
C826
GND
100p F
470p F
12
50V
50V
SPK_ R
13
+3.3 V_S TBY
TP213 6
P_+5 V
TP213 5
SDA2_3.3 V
READ Y
SCL2_3.3 V
C804
0 . 1 uF
16V
GPIO TB D
I R
CEC_ 0
IC100
FLI10610H-AA
A18
AD19
HDMI4_5V_DE T
VXI_CLK
VXO_CLK
C18
AE19
VXI_DE
VXO_DE
B18
AG18
VXI _VS
VXO_VS
D18
AF18
+3.3 V_S TBY
RGB_LINK
VXI _HS
VXO_HS
E19
AF15
VXI_D 0
VXO_D0
COMP1_LIN K
A17
AH16
VXI_D 1
VXO_D1
SIDE_CVBS_LIN K
B17
AJ16
MODULE_SER_CL K
AT24C16AN-10SI-2. 7
VXI_D 2
VXO_D2
C17
AE15
VXI_D 3
VXO_D3
MODULE_SER_DA T A
D17
AE16
VCC
VXI_D 4
VXO_D4
C81 9
8
F17
AF16
0.1uF
SW_RESE T
16 V
A16
VXI_D 5
VXO_D5
AG16
WP
HDMI_SW_E Q
7
VXI_D 6
VXO_D6
B16
AH17
R805 1
VXI_D 7
VXO_D7
22
SC L
C16
AJ17
6
VXI_D 8
VXO_D8
D16
AE17
BOOSTE R
R805 3
22
SD A
VXI_D 9
VXO_D9
5
D19
AF17
VXI_D10
VXO_D10
E16
AG17
VXI_D11
VXO_D11
SIDE_S_S W
A15
AH18
VXI_D12
VXO_D12
B15
AJ18
DTV/MNT_SWITCH
VXI_D13
VXO_D13
C15
AD15
FE_RESE T
VXI_D14
VXO_D14
D15
AE18
VXI_D15
VXO_D15
E15
+3.3V_DOUGLA S
VXI_D16
A14
VXI_D17
B14
A22
VXI_D18
REF_CL K
C14
A23
VXI_D19
XTAL_I N
HDMI2_5V_DE T
D14
E12
HDMI1_5V_DE T
VXI_D20
CLKOUT
E14
F21
HDMI3_5V_DE T
VXI_D21
OBUFC_CL K
E17
HP_D ET_S /W_2
VXI_D22
E18
HP_D ET_S /W_4
VXI_D23
F7
NC_1
F8
NC_2
C27
F9
TESTMODE 0
NC_3
C26
F10
TESTMODE 1
NC_4
F11
NC_5
K6
For CHAPLI N
SIF_IN
NC_ 6
For DOUG LAS
HIGH:Writable
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATE S
SPECIAL FEATURES IMPORTANT FOR PRO TECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC .
CPL_DDR2_D[0-31 ]
CPL_DDR2_DQS2_ N
R77 8
10
10
DDR2_DQS2_ N
CPL_DDR2_DQS2_ P
R77 9
DDR2_DQS2_ P
CPL_DDR2_D[18 ]
R78 0
10
DDR2_D[18 ]
10
CPL_DDR2_D[19 ]
R78 1
DDR2_D[19 ]
CPL_DDR2_DM[0-3 ]
CPL_DDR2_DM[2 ]
R78 2
CPL_DDR2_DM[3 ]
10
DDR2_DM[2 ]
CPL_DDR2_D[22 ]
R78 3
10
DDR2_D[22 ]
DDR2_DM[3 ]
CPL_DDR2_DM[0 ]
R78 4
CPL_DDR2_D[17 ]
10
DDR2_D[17 ]
CPL_DDR2_DM[1 ]
CPL_DDR2_D[20 ]
R78 5
10
DDR2_D[20 ]
DDR2_DM[0 ]
DDR2_DM[1 ]
DDR2_DM[0-3 ]
R78 6
CPL_DDR2_D[21 ]
10
DDR2_D[21 ]
CPL_DDR2_D[16 ]
R78 7
10
DDR2_D[16 ]
R78 8
CPL_DDR2_D[23 ]
10
DDR2_D[23 ]
CPL_DDR2_DQS3_ N
R70 6
10
R70 3
10
DDR2_DQS3_ N
CPL_DDR2_DQS3_ P
DDR2_DQS3_ P
CPL_DDR2_D[26 ]
R70 1
10
DDR2_D[26 ]
R70 2
10
CPL_DDR2_D[27 ]
DDR2_D[27 ]
AR71 6
10
1/16 W
CPL_DDR2_D[30 ]
DDR2_D[30 ]
CPL_DDR2_D[25 ]
DDR2_D[25 ]
CPL_DDR2_D[28 ]
DDR2_D[28 ]
AR70 7
10
1/16 W
CPL_DDR2_D[29 ]
DDR2_D[29 ]
CPL_DDR2_D[24 ]
DDR2_D[24 ]
CPL_DDR2_D[31 ]
DDR2_D[31 ]
CPL_DDR2_D[5 ]
R78 9
10
DDR2_D[5 ]
CPL_DDR2_D[0 ]
R79 0
10
DDR2_D[0 ]
CPL_DDR2_D[7 ]
R79 1
10
DDR2_D[7 ]
R79 2
10
CPL_DDR2_DQS0_ N
R79 3
10
DDR2_DQS0_ N
CPL_DDR2_DQS0_ P
CPL_DDR2_D[2 ]
R79 4
10
DDR2_D[2 ]
DDR2_DQS0_ P
R79 5
10
10
R77 7
DDR2_ODT_ T
DDR2_OD T
10
CPL_DDR2_D[3 ]
R79 6
DDR2_D[3 ]
CPL_DDR2_D[6 ]
R79 7
10
DDR2_D[6 ]
CPL_DDR2_D[1 ]
R79 8
10
DDR2_D[1 ]
CPL_DDR2_D[4 ]
R79 9
10
DDR2_D[4 ]
AR71 0
10
1/16 W
DDR2_D[13 ]
CPL_DDR2_D[13 ]
CPL_DDR2_D[8 ]
DDR2_D[8 ]
DDR2_D[15 ]
CPL_DDR2_D[15 ]
CPL_DDR2_DQS1_ N
R71 0
10
DDR2_DQS1_ N
CPL_DDR2_DQS1_ P
R70 5
10
DDR2_D[10 ]
DDR2_DQS1_ P
CPL_DDR2_D[10 ]
R70 4
10
DDR2_D[11 ]
CPL_DDR2_D[11 ]
R70 7
10
AR71 1
10
1/16 W
CPL_DDR2_D[14 ]
DDR2_D[14 ]
DDR2_D[9 ]
CPL_DDR2_D[9 ]
CPL_DDR2_D[12 ]
DDR2_D[12 ]
AR70 8
C74 2
CPL_DDR2_A[0-12 ]
10
DDR2_D[0-31 ]
1uF
1/16 W
CPL_DDR2_A[10 ]
DDR2_A[10 ]
6.3V
CPL_DDR2_A[3 ]
DDR2_A[3 ]
CPL_DDR2_A[7 ]
DDR2_A[7 ]
CPL_DDR2_A[12 ]
DDR2_A[12 ]
AR70 6
10
1/16 W
CPL_DDR2_A[2 ]
DDR2_A[2 ]
CPL_DDR2_A[9 ]
DDR2_A[9 ]
CPL_DDR2_A[5 ]
DDR2_A[5 ]
CPL_DDR2_BA 1
DDR2_BA 1
AR71 7
10
1/16 W
CPL_DDR2_WE_ N
DDR2_WE_ N
CPL_DDR2_A[1 ]
DDR2_A[1 ]
CPL_DDR2_BA 0
DDR2_BA 0
CPL_DDR2_CK E
DDR2_CK E
R71 6
10
CPL_DDR2_CK_ N
DDR2_CK_ N
R71 5
10
CPL_DDR2_C K
R71 4
10
DDR2_C K
CPL_DDR2_A[0 ]
DDR2_A[0 ]
CPL_DDR2_A[4 ]
R71 3
10
DDR2_A[4 ]
AR70 4
10
1/16 W
CPL_DDR2_A[8 ]
DDR2_A[8 ]
CPL_DDR2_CAS_ N
DDR2_CAS_ N
CPL_DDR2_A[11 ]
DDR2_A[11]
CPL_DDR2_A[6 ]
DDR2_A[6 ]
DDR2_A[0-12 ]
R72 4
10
CPL_DDR2_CS_ N
DDR2_CS_ N
CPL_DDR2_RAS_ N
R72 5
10
DDR2_RAS_ N
DDR2
P_+5 V
+3.3 V_S TBY
R805 0
10 K
R806 3
10 K
IC803
KIA7029AF
I
1
3 O
2
C81 5
G
C81 3
OP T
0.1uF
16 V
C81 4
0.1uF
16 V
+3.3 V_S TBY
+3.3 V_S TBY
+3.3V_S TBY
R805 8
10K
R809 4
C82 5
C81 8
VDD33V
GPIOD2 /P10 /AD4
10K
10u F
0.1uF
1
33
READ Y
6.3V
16 V
GND
GPIOD3 /P11/AD5
2
32
OSC O
GPIOD4 /P12 /AD6
3
IC802
31
3.3V_O N
R809 3
10K
OS CI
GPIOD5 /P13 /AD7
READ Y
4
30
RL_ON/PWR_ONOF F
WT61 P 8-R N440W T
GPIOB6/SSD A
GPIOD6/TXD 2
R807 1
5
29
22
UCOM_T X
GPIOB5/SSC L
GPIOD7/RXD 2
6
28
UCOM_R X
R804 4
GPI OB4/P05
GP IOA0/PWM4/P00
22
7
27
HDMI_SEL1
GPI OB3/P04
GP IOA1/PWM5/P01
8
26
HDMI_SEL2
R804 0
GPIOB2/IR
GP IOA2/PWM6/P02
R805 4
4.7K
9
25
100
1.8V_DOUGLAS_E N
R806 9
GPIOB1/IRQ3/CE C
GP IOA3/PWM7/P03
100
10
24
1.26V_DOUGLAS_E N
R808 7
GPIOB0/IRQ2
GPIOA4/DSCL 2
0
11
23
READY
+3.3 V_S TBY
R809 2
100
MUTE_LINE_MNTOUT
IC801
A0
R807 0
1
6.8K
A1
R809 5
2
6.8K
+3.3 V_S TBY
A2
3
R807 3
P_+5 V
10 K
GN D
4
R806 8
10 K
GPIO, Sub-Micom
LGE Internal Use Only
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