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Alinx AC7A200 User Manual

Artix-7 fpga core board system on module
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ARTIX-7 FPGA
Core Board
AC7A200
System on Module

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Summary of Contents for Alinx AC7A200

  • Page 1 ARTIX-7 FPGA Core Board AC7A200 System on Module...

  • Page 2: Version Record

    ARTIX-7 FPGA Development Board AC7A200 User Manual Version Record Version Date Release By Description Rev 1.0 2020-06-28 Rachel Zhou First Release www.alinx.com 2 / 31...

  • Page 3: Table Of Contents

    ARTIX-7 FPGA Development Board AC7A200 User Manual Table of Contents Version Record...................... 2 Part 1: AC7A200 Core Board Introduction............4 Part 2: FPGA Chip....................6 Part 3: Active Differential Crystal................ 8 Part 3.1: 200Mhz Active Differential clock..........8 Part 3.2: 125MHz Active Differential Crystal..........9 Part 4: DDR3 DRAM...................

  • Page 4: Part 1: Ac7A200 Core Board Introduction

    FPGA and DDR3 is up to 25Gb; such a configuration can meet the needs of high bandwidth data processing. The AC7A200 core board expands 180 standard IO ports of 3.3V level, 15 standard IO ports of 1.5V level, and 4 pairs of GTP high speed RX/TX differential signals.
  • Page 5 ARTIX-7 FPGA Development Board AC7A200 User Manual Figure 1-1: AC7A200 Core Board (Front View) Figure 1-2: AC7A200 Core Board (Rear View) www.alinx.com 5 / 31...

  • Page 6: Part 2: Fpga Chip

    ARTIX-7 FPGA Development Board AC7A200 User Manual Part 2: FPGA Chip As mentioned above, the FPGA model we use is XC7A200T-2FBG484I, which belongs to Xilinx's Artix-7 series. The speed grade is 2, and the temperature grade is industry grade. This model is a FGG484 package with 484 pins.
  • Page 7 CCAUX each BANK of FPGA, including BANK0, BANK13~16, BANK34~35. On AC7A200 FPGA core board, BANK34 and BANK35 need to be connected to DDR3, the voltage connection of BANK is 1.5V, and the voltage of other BANK is 3.3V. The V of BANK15 and BANK16 is powered by the LDO, and can be changed by replacing the LDO chip.

  • Page 8: Part 3: Active Differential Crystal

    ARTIX-7 FPGA Development Board AC7A200 User Manual Part 3: Active Differential Crystal The AC7A200 core board is equipped with two Sitime active differential crystals, one is 200MHz, the model is SiT9102-200.00MHz, the system main clock for FPGA and used to generate DDR3 control clock; the other is 125MHz, model is SiT9102 -125MHz, reference clock input for GTP transceivers.

  • Page 9: Part 3.2: 125Mhz Active Differential Crystal

    ARTIX-7 FPGA Development Board AC7A200 User Manual 200Mhz Differential Clock Pin Assignment Signal Name FPGA PIN SYS_CLK_P SYS_CLK_N Part 3.2: 125MHz Active Differential Crystal G2 in Figure 3-3 is the 125MHz active differential crystal, which is the reference input clock provided to the GTP module inside the FPGA. The crystal output is connected to the GTP BANK216 clock pins MGTREFCLK0P (F6) and MGTREFCLK0N (E6) of the FPGA.
  • Page 10 ARTIX-7 FPGA Development Board AC7A200 User Manual 125MHz Differential Clock Pin Assignment Net Name FPGA PIN MGT_CLK0_P MGT_CLK0_N www.alinx.com 10 / 31...

  • Page 11: Part 4: Ddr3 Dram

    ARTIX-7 FPGA Development Board AC7A200 User Manual Part 4: DDR3 DRAM The FPGA core board AC7A200 is equipped with two Micron 4Gbit (512MB) DDR3 chips (8Gbit in totally), model is MT41J256M16HA-125 (compatible with MT41K256M16HA-125). The DDR3 SDRAM has a maximum operating speed of 400MHz (data rate 800Mbps).
  • Page 12 ARTIX-7 FPGA Development Board AC7A200 User Manual Figure 4-2: The DDR3 on the Core Board DDR3 DRAM pin assignment: Net Name FPGA PIN Name FPGA P/N DDR3_DQS0_P IO_L3P_T0_DQS_AD5P_35 DDR3_DQS0_N IO_L3N_T0_DQS_AD5N_35 DDR3_DQS1_P IO_L9P_T1_DQS_AD7P_35 DDR3_DQS1_N IO_L9N_T1_DQS_AD7N_35 DDR3_DQS2_P IO_L15P_T2_DQS_35 DDR3_DQS2_N IO_L15N_T2_DQS_35 DDR3_DQS3_P IO_L21P_T3_DQS_35...
  • Page 13 ARTIX-7 FPGA Development Board AC7A200 User Manual DDR3_DQ [11] IO_L10N_T1_AD15N_35 DDR3_DQ [12] IO_L7N_T1_AD6N_35 DDR3_DQ [13] IO_L10P_T1_AD15P_35 DDR3_DQ [14] IO_L7P_T1_AD6P_35 DDR3_DQ [15] IO_L12P_T1_MRCC_35 DDR3_DQ [16] IO_L18N_T2_35 DDR3_DQ [17] IO_L16P_T2_35 DDR3_DQ [18] IO_L14P_T2_SRCC_35 DDR3_DQ [19] IO_L17N_T2_35 DDR3_DQ [20] IO_L14N_T2_SRCC_35 DDR3_DQ [21] IO_L17P_T2_35...
  • Page 14 ARTIX-7 FPGA Development Board AC7A200 User Manual DDR3_A[11] IO_L4P_T0_34 DDR3_A[12] IO_L4N_T0_34 DDR3_A[13] IO_L1N_T0_34 DDR3_A[14] IO_L6N_T0_VREF_34 DDR3_BA[0] IO_L9N_T1_DQS_34 DDR3_BA[1] IO_L9P_T1_DQS_34 DDR3_BA[2] IO_L11P_T1_SRCC_34 DDR3_S0 IO_L8P_T1_34 DDR3_RAS IO_L12P_T1_MRCC_34 DDR3_CAS IO_L12N_T1_MRCC_34 DDR3_WE IO_L7P_T1_34 DDR3_ODT IO_L14N_T2_SRCC_34 DDR3_RESET IO_L15P_T2_DQS_34 DDR3_CLK_P IO_L3P_T0_DQS_34 DDR3_CLK_N IO_L3N_T0_DQS_34 DDR3_CKE IO_L14P_T2_SRCC_34 www.alinx.com...

  • Page 15: Part 5: Qspi Flash

    ARTIX-7 FPGA Development Board AC7A200 User Manual Part 5: QSPI Flash The FPGA core board AC7A200 is equipped with one 128Mbit QSPI FLASH, and the model is N25Q128, which uses the 3.3V CMOS voltage standard. Due to the non-volatile nature of QSPI FLASH, it can be used as a boot device for the system to store the boot image of the system.
  • Page 16 ARTIX-7 FPGA Development Board AC7A200 User Manual QSPI Flash pin assignments: Net Name FPGA PIN Name FPGA P/N QSPI_CLK CCLK_0 QSPI_CS IO_L6P_T0_FCS_B_14 QSPI_DQ0 IO_L1P_T0_D00_MOSI_14 QSPI_DQ1 IO_L1N_T0_D01_DIN_14 QSPI_DQ2 IO_L2P_T0_D02_14 QSPI_DQ3 IO_L2N_T0_D03_14 Figure 5-2: QSPI FLASH on the Core Board www.alinx.com 16 / 31...

  • Page 17: Part 6: Led Light On Core Board

    ARTIX-7 FPGA Development Board AC7A200 User Manual Part 6: LED Light on Core Board There are 3 red LED lights on the AC7A200 FPGA core board, one of which is the power indicator light (PWR), one is the configuration LED light (DONE), and one is the user LED light.
  • Page 18 ARTIX-7 FPGA Development Board AC7A200 User Manual Figure 6-2: LED lights on the Core Board User LEDs Pin Assignment Signal Name FPGA Pin Name FPGA Pin Number Description LED1 IO_L15N_T2_DQS_34 User LED www.alinx.com 18 / 31...

  • Page 19: Part 7: Jtag Interface

    ARTIX-7 FPGA Development Board AC7A200 User Manual Part 7: JTAG Interface The JTAG test socket J1 is reserved on the AC7A200 core board for JTAG download and debugging when the core board is used alone. Figure 7-1 is the schematic part of the JTAG port, which involves TMS, TDI, TDO, TCK. , GND, +3.3V these six signals.

  • Page 20: Part 8: Power Interface On The Core Board

    ARTIX-7 FPGA Development Board AC7A200 User Manual Part 8: Power Interface on the Core Board In order to make the AC7A200 FPGA core board work alone, the core board is reserved 2-pin power supply interface J2. If the user wants to debug the function of the core board separately (without the carrier board), the external device needs to provide +5V to supply power to the core board.

  • Page 21: Part 9: Board To Board Connectors Pin Assignment

    ARTIX-7 FPGA Development Board AC7A200 User Manual Part 9: Board to Board Connectors pin assignment The core board has a total of four high-speed board to board connectors. The core board uses four 80-pin inter-board connectors to connect to the carrier board.
  • Page 22 ARTIX-7 FPGA Development Board AC7A200 User Manual PIN23 B13_L5_N AA14 3.3V PIN24 B13_L1_N AA16 3.3V PIN25 B13_L7_P AB11 3.3V PIN26 B13_L2_P AB16 3.3V PIN27 B13_L7_P AB12 3.3V PIN28 B13_L2_N AB17 3.3V Ground Ground PIN29 PIN30 PIN31 B13_L3_P AA13 3.3V PIN32 B13_L6_P 3.3V...
  • Page 23 ARTIX-7 FPGA Development Board AC7A200 User Manual Figure 9-1: Board to Board Connectors CON1 on the Core Board Board to Board Connectors CON2 The 80-pin female connection header CON2 is used to extend the normal IO of the BANK13 and BANK14 of the FPGA. The voltage standards of both BANKs are 3.3V.
  • Page 24 ARTIX-7 FPGA Development Board AC7A200 User Manual PIN33 B13_L9_P AA10 3.3V PIN34 B13_IO0 3.3V PIN35 B13_L8_N AB10 3.3V PIN36 B14_L7_N 3.3V PIN37 B13_L8_P 3.3V PIN38 B14_L7_P 3.3V PIN39 Ground PIN40 Ground PIN41 B14_L11_N 3.3V PIN42 B14_L4_P 3.3V PIN43 B14_L11_P 3.3V...
  • Page 25 ARTIX-7 FPGA Development Board AC7A200 User Manual Board to Board Connectors CON3 The 80-pin connector CON3 is used to extend the normal IO of the BANK15 and BANK16 of the FPGA. In addition, four JTAG signals are also connected to the carrier board via the CON3 connector. The voltage standards of BANK15 and BANK16 can be adjusted by an LDO chip.
  • Page 26 ARTIX-7 FPGA Development Board AC7A200 User Manual PIN43 B15_L19_N 3.3V PIN44 B15_L15_P 3.3V PIN45 B15_L20_P 3.3V PIN46 B15_L6_N 3.3V PIN47 B15_L20_N 3.3V PIN48 B15_L6_P 3.3V PIN49 Ground PIN50 Ground PIN51 B15_L14_P 3.3V PIN52 B15_L13_N 3.3V PIN53 B15_L14_N 3.3V PIN54 B15_L13_P 3.3V...
  • Page 27 ARTIX-7 FPGA Development Board AC7A200 User Manual of the IO port of BANK16 can be adjusted by an LDO chip. The default installed LDO is 3.3V. If the user wants to output other standard levels, it can be replaced by a suitable LDO. The high-speed data and clock signals of the GTP are strictly differential routed on the core board.
  • Page 28 ARTIX-7 FPGA Development Board AC7A200 User Manual PIN49 Ground PIN50 Ground PIN51 B16_L9_P 3.3V PIN52 B16_L10_P 3.3V PIN53 B16_L9_N 3.3V PIN54 B16_L10_N 3.3V PIN55 B16_L11_P 3.3V PIN56 B16_L12_P 3.3V PIN57 B16_L11_N 3.3V PIN58 B16_L12_N 3.3V PIN59 Ground PIN60 Ground PIN61 B16_L13_P 3.3V...

  • Page 29: Part 10: Power Supply

    ARTIX-7 FPGA Development Board AC7A200 User Manual Part 10: Power Supply The AC7A200 FPGA core board is powered by DC5V via carrier board, and it is powered by the Mini USB interface when it is used alone. Please be careful not to supply power by the Mini USB and the carrier board at the same time to avoid damage.
  • Page 30 1.0V-> MGTAVCC -> MGTAVTT, the circuit design to ensure the normal operation of the chip. The power circuit on the AC7A200 FPGA core board is shown in Figure 10-2: Figure 10-2: Power Supply on the AC7A200 FPGA Core Board www.alinx.com...

  • Page 31: Part 11: Size Dimension

    ARTIX-7 FPGA Development Board AC7A200 User Manual Part 11: Size Dimension Figure 11-1: AC7A200 FPGA Core board (Top View) Figure 11-2: AC7A200 FPGA Core board (Bottom View) www.alinx.com 31 / 31...

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