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Alinx AC7A035 Manual

Artix-7 fpga core board system on module
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ARTIX-7 FPGA
Core Board
AC7A035
System on Module

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Summary of Contents for Alinx AC7A035

  • Page 1 ARTIX-7 FPGA Core Board AC7A035 System on Module...

  • Page 2: Version Record

    ARTIX-7 FPGA Development Board AC7A035 User Manual Version Record Version Date Release By Description Rev 1.0 2020-06-28 Rachel Zhou First Release www.alinx.com 2 / 29...

  • Page 3: Table Of Contents

    ARTIX-7 FPGA Development Board AC7A035 User Manual Table of Contents Version Record ..................2 Part 1: AC7A035 Core Board Introduction ..........4 Part 2: FPGA Chip ..................6 Part 3: Active Differential Crystal ............... 8 Part 3.1: 200Mhz Active Differential clock ........... 8 Part 3.2: 125MHz Active Differential Crystal ........

  • Page 4: Part 1: Ac7A035 Core Board Introduction

    FPGA and DDR3 is up to 25Gb; such a configuration can meet the needs of high bandwidth data processing. The AC7A035 core board expands 146 standard IO ports of 3.3V level, 15 standard IO ports of 1.5V level, and 4 pairs of GTP high speed RX/TX differential signals.
  • Page 5 ARTIX-7 FPGA Development Board AC7A035 User Manual Figure 1-1: AC7A035 Core Board (Front View) Figure 1-2: AC7A035 Core Board (Rear View) www.alinx.com 5 / 29...

  • Page 6: Part 2: Fpga Chip

    ARTIX-7 FPGA Development Board AC7A035 User Manual Part 2: FPGA Chip As mentioned above, the FPGA model we use is XC7A35T-2FGG484I, which belongs to Xilinx's Artix-7 series. The speed grade is 2, and the temperature grade is industry grade. This model is a FGG484 package with 484 pins.
  • Page 7 CCAUX each BANK of FPGA, including BANK0, BANK13~16, BANK34~35. On AC7A035 FPGA core board, BANK34 and BANK35 need to be connected to DDR3, the voltage connection of BANK is 1.5V, and the voltage of other BANK is 3.3V. The V of BANK15 and BANK16 is powered by the LDO, and can be changed by replacing the LDO chip.

  • Page 8: Part 3: Active Differential Crystal

    ARTIX-7 FPGA Development Board AC7A035 User Manual Part 3: Active Differential Crystal The AC7A035 core board is equipped with two Sitime active differential crystals, one is 200MHz, the model is SiT9102-200.00MHz, the system main clock for FPGA and used to generate DDR3 control clock; the other is 125MHz, model is SiT9102 -125MHz, reference clock input for GTP transceivers.

  • Page 9: Part 3.2: 125Mhz Active Differential Crystal

    ARTIX-7 FPGA Development Board AC7A035 User Manual 200Mhz Differential Clock Pin Assignment Signal Name FPGA PIN SYS_CLK_P SYS_CLK_N Part 3.2: 125MHz Active Differential Crystal G2 in Figure 3-3 is the 125MHz active differential crystal, which is the reference input clock provided to the GTP module inside the FPGA. The crystal output is connected to the GTP BANK216 clock pins MGTREFCLK0P (F6) and MGTREFCLK0N (E6) of the FPGA.

  • Page 10: Part 4: Ddr3 Dram

    MGT_CLK0_P MGT_CLK0_N Part 4: DDR3 DRAM The FPGA core board AC7A035 is equipped with two Micron 4Gbit (512MB) DDR3 chips (8Gbit in totally), model is MT41J256M16HA-125 (compatible with MT41K256M16HA-125). The DDR3 SDRAM has a maximum operating speed of 400MHz (data rate 800Mbps). The DDR3 memory system is directly connected to the memory interface of the BANK 34 and BANK35 of the FPGA.
  • Page 11 ARTIX-7 FPGA Development Board AC7A035 User Manual Data[31:16] DDR3 (MT41J256M16 BANK FPGA 34/35 Addr/control DDR3 Data[15:0] (MT41J256M16 Figure 4-1: The DDR3 DRAM Schematic Figure 4-2: The DDR3 on the Core Board DDR3 DRAM pin assignment: Net Name FPGA PIN Name...
  • Page 12 ARTIX-7 FPGA Development Board AC7A035 User Manual DDR3_DQS1_N IO_L9N_T1_DQS_AD7N_35 DDR3_DQS2_P IO_L15P_T2_DQS_35 DDR3_DQS2_N IO_L15N_T2_DQS_35 DDR3_DQS3_P IO_L21P_T3_DQS_35 DDR3_DQS3_N IO_L21N_T3_DQS_35 DDR3_DQ[0] IO_L2P_T0_AD12P_35 DDR3_DQ [1] IO_L5P_T0_AD13P_35 DDR3_DQ [2] IO_L1N_T0_AD4N_35 DDR3_DQ [3] IO_L6P_T0_35 DDR3_DQ [4] IO_L2N_T0_AD12N_35 DDR3_DQ [5] IO_L5N_T0_AD13N_35 DDR3_DQ [6] IO_L1P_T0_AD4P_35 DDR3_DQ [7] IO_L4P_T0_35...

  • Page 13: Part 5: Qspi Flash

    IO_L9P_T1_DQS_34 DDR3_BA[2] IO_L11P_T1_SRCC_34 DDR3_S0 IO_L8P_T1_34 DDR3_RAS IO_L12P_T1_MRCC_34 DDR3_CAS IO_L12N_T1_MRCC_34 DDR3_WE IO_L7P_T1_34 DDR3_ODT IO_L14N_T2_SRCC_34 DDR3_RESET IO_L15P_T2_DQS_34 DDR3_CLK_P IO_L3P_T0_DQS_34 DDR3_CLK_N IO_L3N_T0_DQS_34 DDR3_CKE IO_L14P_T2_SRCC_34 Part 5: QSPI Flash The FPGA core board AC7A035 is equipped with one 128Mbit QSPI www.alinx.com 13 / 29...
  • Page 14 ARTIX-7 FPGA Development Board AC7A035 User Manual FLASH, and the model is N25Q128, which uses the 3.3V CMOS voltage standard. Due to the non-volatile nature of QSPI FLASH, it can be used as a boot device for the system to store the boot image of the system. These images mainly include FPGA bit files, ARM application code, soft core application code and other user data files.

  • Page 15: Part 6: Led Light On Core Board

    ARTIX-7 FPGA Development Board AC7A035 User Manual QSPI Flash pin assignments: Net Name FPGA PIN Name FPGA P/N QSPI_CLK CCLK_0 QSPI_CS IO_L6P_T0_FCS_B_14 QSPI_DQ0 IO_L1P_T0_D00_MOSI_14 QSPI_DQ1 IO_L1N_T0_D01_DIN_14 QSPI_DQ2 IO_L2P_T0_D02_14 QSPI_DQ3 IO_L2N_T0_D03_14 Figure 5-2: QSPI FLASH on the Core Board Part 6: LED Light on Core Board...
  • Page 16 ARTIX-7 FPGA Development Board AC7A035 User Manual Figure 6-1: LED lights on the Core Board Schematic Figure 6-2: LED lights on the Core Board www.alinx.com 16 / 29...

  • Page 17: Part 7: Jtag Interface

    ARTIX-7 FPGA Development Board AC7A035 User Manual User LEDs Pin Assignment Signal Name FPGA Pin Name FPGA Pin Number Description LED1 IO_L15N_T2_DQS_34 User LED Part 7: JTAG Interface The JTAG test socket J1 is reserved on the AC7A200 core board for JTAG download and debugging when the core board is used alone.

  • Page 18: Part 8: Power Interface On The Core Board

    ARTIX-7 FPGA Development Board AC7A035 User Manual Part 8: Power Interface on the Core Board In order to make the AC7A200 FPGA core board work alone, the core board is reserved 2-pin power supply interface J2. If the user wants to debug the function of the core board separately (without the carrier board), the external device needs to provide +5V to supply power to the core board.
  • Page 19 ARTIX-7 FPGA Development Board AC7A035 User Manual Board to Board Connectors CON1 The 80-pin board to board connectors CON1, which are used to connect with the VCCIN power supply (+5V) and ground on the carrier board, extend the normal IOs of the FPGA. It should be noted here that 15 pins of CON1 are connected to the IO port of BANK34, because the BANK34 connection is connected to DDR3.
  • Page 20 ARTIX-7 FPGA Development Board AC7A035 User Manual PIN39 Ground PIN40 Ground PIN41 B34_L18_N 1.5V PIN42 B34_L21_N 1.5V PIN43 B34_L18_P 1.5V PIN44 B34_L21_P 1.5V PIN45 B34_L19_P 1.5V PIN46 B34_L22_P 1.5V PIN47 B34_L19_N 1.5V PIN48 B34_L22_N 1.5V PIN49 Ground PIN50 Ground PIN51...
  • Page 21 ARTIX-7 FPGA Development Board AC7A035 User Manual BANKs are 3.3V. The IOs of BANK 13 is not existed in XC7A35T chipset, it is designed to compatible with XC7A100T/XC7A200T chipset, please do not use these IO in AC7A035 board. Pin Assignment of Board to Board Connectors CON2...
  • Page 22 ARTIX-7 FPGA Development Board AC7A035 User Manual PIN53 B14_L5_P 3.3V PIN54 B14_L12_P 3.3V PIN55 B14_L18_N 3.3V PIN56 B14_L13_N 3.3V PIN57 B14_L18_P 3.3V PIN58 B14_L13_P 3.3V PIN59 Ground PIN60 Ground PIN61 B13_L17_P 3.3V PIN62 B14_L3_N 3.3V PIN63 B13_L17_N 3.3V PIN64 B14_L3_P 3.3V...
  • Page 23 ARTIX-7 FPGA Development Board AC7A035 User Manual CON3 FPGA Voltage CON3 FPGA Voltage Name Level Name Level PIN1 B15_IO0 3.3V PIN2 B15_IO25 3.3V PIN3 B16_IO0 3.3V PIN4 B16_IO25 3.3V PIN5 B15_L4_P 3.3V PIN6 B16_L21_N 3.3V PIN7 B15_L4_N 3.3V PIN8 B16_L21_P 3.3V...
  • Page 24 ARTIX-7 FPGA Development Board AC7A035 User Manual PIN63 B15_L23_N 3.3V PIN64 B15_L18_N 3.3V PIN65 B15_L22_P 3.3V PIN66 B15_L17_N 3.3V PIN67 B15_L22_N 3.3V PIN68 B15_L17_P 3.3V PIN69 Ground PIN70 Ground PIN71 B15_L24_P 3.3V PIN72 B15_L16_P 3.3V PIN73 B15_L24_N 3.3V PIN74 B15_L16_N 3.3V...
  • Page 25 ARTIX-7 FPGA Development Board AC7A035 User Manual PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 Ground Ground PIN9 PIN10 MGT_TX2_P Diff PIN11 PIN12 MGT_TX2_N Diff PIN13 PIN14 Ground Ground PIN15 PIN16 MGT_TX3_P Diff MGT_RX2_P Diff PIN17 PIN18 MGT_TX3_N Diff MGT_RX2_N Diff PIN19...

  • Page 26: Part 10: Power Supply

    Figure 9-4: Board to Board Connectors CON4 on the Core Board Part 10: Power Supply The AC7A035 FPGA core board is powered by DC5V via carrier board, and it is powered by the J2 interface when it is used alone.
  • Page 27 ARTIX-7 FPGA Development Board AC7A035 User Manual Figure 10-1：Power Supply on core board schematic The core board is powered by +5V and converted to +3.3V, +1.5V, +1.8V, +1.0V four-way power supply through three DC/DC power supply chip TLV62130RGT. The current of +1.0V can be up to 6A, and the other three output currents can be up to 3A.
  • Page 28 1.0V-> MGTAVCC -> MGTAVTT, the circuit design to ensure the normal operation of the chip. The power circuit on the AC7A035 FPGA core board is shown in Figure 10-2: Figure 10-2: Power Supply on the AC7A035 FPGA Core Board www.alinx.com...

  • Page 29: Part 11: Size Dimension

    ARTIX-7 FPGA Development Board AC7A035 User Manual Part 11: Size Dimension Figure 11-1: AC7A035 FPGA Core board (Top View) Figure 11-2: AC7A035 FPGA Core board (Bottom View) www.alinx.com 29 / 29...

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