Table of Contents
Advertisement
U5 92L31000250100 : CPU ( TS2501 ) ( 3/4 )
PIN DESCRIPTION
Signal Name
Shared Signal
SD_CKE
GPIO_B[0]
SD_CLK
GPO
SD_nCS
SD_nCLK/
GPIO_B[1]
XA[21:20]
DQM[0:1]
XA[19:18]
DQS[1:0]
XA[17]
ND_CLE
XA[16]
SD_nRAS
XA[15]
SD_nCAS
XA[14]
SD_BA[1]
XA[13]
SD_BA[0]
XA[12:7]
XA[6:0]
XA[15:9]
XA[8:4]
XA[3:0]
NCS[3:0]
ND_nOE[3:0] /
GPIO_B[5:2]
ND_nWE
GPIO_B[7]
nWE
nOE
READY
GPIO_B[0]
SD_CKE
GPIO_D[21:1
FGPIO[14:11] /
8]
CISD[7:4]
GPIO_D[17]
FGPIO[10] /
SCL / CISHS
GPIO_D[16]
FGPIO[9] /
SDA / CISVS
GPIO_D[15]
FGPIO[9] /
CISCLK
ADIN_0
-
ADIN_2
-
ADIN_4
-
XIN
-
XOUT
-
XFILT
-
XTIN
-
XTOUT
-
MODE1
-
PKG1
-
nRESET
-
TDI
-
TMS
-
TCK
-
TDO
-
nTRST
-
Pin #
Type
External Memory Interface Pins
56
Input/Output
SDRAM Clock Enable signal. Active high. / GPIO_B[0]
44
Input/Output
SDRAM Clock / GPO. SD_CLK can be used as a general purpose output.
Refer to section "MEMORY CONTROLLER".
(MCFG register Bit[3] and Bit [1])
46
Input/Output
Chip select signal for SDRAM, Active low / Inverted SD_CLK for DDR SDRAM
/ GPIO_B[1]
43:42
Input/Output
External Bus Address Bit [21:20] / Data I/O Mask 0, 1
40:39
Input/Output
External Bus Address Bit [19:18] / DDR SDRAM / GPIO_B[1]
38
Input/Output
External Bus Address Bit [17] / CLE for NAND Flash
37
Input/Output
External Bus Address Bit [16] / SDRAM RAS signal / ALE for NAND Flash
36
Input/Output
External Bus Address Bit [15] / SDRAM CAS signal
35
Input/Output
External Bus Address Bit [14] / SDRAM Bank Address 1
34
Input/Output
External Bus Address Bit [13] / SDRAM Bank Address 0
31:26
Input/Output
External Bus Address Bit [12:0]
23:17
15:9
Input/Output
External Bus Address Bit [15:0]
6:2
128:125
50:47
Input/Output
External Bus Chip Select [3:0] / NAND Flash Output Enable [3:0] /
GPIO_B[5:2]
57
Input/Output
NAND Flash WE. Active low. / GPIO_B[7]
58
Input/Output
Static Memory Write Enable signal. Active low.
59
Input/Output
Static Memory Write Output Enable signal. Active low.
73
Input
Ready information from external device.
SDRAM / Inverted Clock for DDR SDRAM.
56
Input/Output
GPIO[0] / SDRAM clock control
96:93
Input/Output
GPIO_D[21:18] / Fast GPIO bits 14 ~ 11 / Camera Interface Data Inputs
3 ~ 0. Internal pull-up resistors are enabled at reset. GPIO_D[19:18] are
disabled in TS250IT(N.C).
92
Input/Output
GPIO_D[17] / Fast GPIO bit 10 / 12C SCL / Camera Interface Hsync.
91
Input/Output
GPIO_D[16] / Fast GPIO bit 9 / 12C SDA / Camera Interface Vsync.
90
Input/Output
GPIO_D[15] / Fast GPIO bit 8 / Camera Interface Clock
ADC Input Pins
82
Audio Input
General purpose multi-channel ADC input 0
83
Audio Input
General purpose multi-channel ADC input 2
84
Audio Input
General purpose multi-channel ADC input 4
74
Input
Main Crystal Oscillator Input for PLL. 12MHz Crystal must be used if USB
Boot Mode is required. Input voltage must not exceed VDD_OSC
(1.95V max).
75
Ouput
Main Crystal Oscillator Output for PLL
78
Audio Output
PLL filter output
69
Input
Sub Crystal Oscillator Input. 32.768kHz is recommended. Input voltage must
not exceed VDD_OSC (1.95V max).
70
Ouput
Sub Crystal Oscillator Output
Mode Control Pins
98
Input
Mode Setting Input 1. Pull-down for normal operation.
89
Input
Package ID1. Pull-up for normal operation.
72
Input
System Reset. Active low.
JTAG Interface Pins
99
Input
JTAG serial data input for ARM940T
100
Input
JTAG test mode select for ARM940T
101
Input
JTAG test clock for ARM940T
102
Input/Output
JTAG serial data output for ARM940T. External pull-up resistor is required to
prevent floating during normal operation.
103
Input
JTAG reset signal for ARM940T. Active low.
Description-TS2501
Clock Pins
7 – 4
XL-UH4H
Advertisement
Table of Contents
