Philips PDIUSBD12 Product Data page 27

Philips Semiconductors
DMREQ
DMACK_N
RD_N/WR_N
(1)
EOT_N
EOT_N is considered valid when DMACK_N, RD_N/WR_N and EOT_N are all LOW.
Fig 19. Single-cycle DMA timing.
DMREQ
DMACK_N
RD_N/WR_N
Fig 20. Burst DMA timing.
Fig 21. DMA terminated by EOT.
9397 750 09238
Product data
t RHSH
t EL
t RHSH
Rev. 08 — 20 December 2001
USB interface device with parallel bus
t AHRH
t SHAH
t SLRL
t SHAH
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
PDIUSBD12
SV00874
SV00875
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