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Philips Semiconductors
Table 17:
AC characteristics (parallel interface)
Symbol
Parameter
ALE timings
t
ALE HIGH pulse width
LH
t
address valid to ALE LOW time
AVLL
t
ALE LOW to Address transition time
LLAX
Write timings
t
CS_N (DMACK_N) LOW to WR_N LOW time
CLWL
t
WR_N HIGH to CS_N (DMACK_N) HIGH time
WHCH
t
A0 Valid to WR_N LOW time
AVWL
t
WR_N HIGH to A0 transition time
WHAX
t
WR_N LOW pulse width
WL
t
write data setup time
WDSU
t
write data hold time
WDH
t
write cycle time
WC
t
write command to write data
(WC - WD)
Read timings
t
CS_N (DMACK_N) LOW to RD_N LOW time
CLRL
t
RD_N HIGH to CS_N (DMACK_N) HIGH time
RHCH
t
A0 Valid to RD_N LOW time
AVRL
t
RD_N LOW pulse width
RL
t
RD_N LOW to Data Driven time
RLDD
t
RD_N HIGH to Data Hi-Z time
RHDZ
t
read cycle time
RC
t
write command to read data
(WC - RD)
[1]
Can be negative.
[2]
For DMA access only on the module 64
[3]
The t
and t
timings are valid for back-to-back data access only.
WC
RC
Fig 17. ALE timing.
9397 750 09238
Product data
Conditions
th
byte and the second last (EOT-1)byte.
Rev. 08 — 20 December 2001
PDIUSBD12
USB interface device with parallel bus
Min
Max
−
20
−
10
−
10
−
[1]
0
−
5
−
[1]
0
[2]
130
-
−
5
−
20
−
30
−
10
−
[3]
500
600
-
−
[1]
0
[2]
130
-
−
5
−
[1]
0
−
20
−
20
−
20
−
[3]
500
600
-
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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