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Canberra 9660 User Manual

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Model 9660/9660A
ICB Digital Signal
Processor
User's Manual
9231014G

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Summary of Contents for Canberra 9660

  • Page 1 Model 9660/9660A ICB Digital Signal Processor User’s Manual 9231014G...
  • Page 2 Copyright 2007, Canberra Industries, Inc. All rights reserved. The material in this document, including all information, pictures, graphics and text, is the property of Canberra Industries, Inc. and is protected by U.S. copyright laws and international copyright conventions. Canberra expressly grants the purchaser of this product the right to copy any material in this document for the purchaser’s own use,...

  • Page 3: Table Of Contents

    Defining a Detector Input........19 ICB DSP 9660 Setup Parameters ....... . . 21 9660 Default Values .
  • Page 4 Rise Time and Flat Top Adjustments....... 63 Model 9660-9660A ICB Digital Signal Processor...
  • Page 5 Pole/Zero Matching - Supplementary Information ......66 Using a Square Wave Generator ....... . 66 Pole/Zero Matching and “Wrap Around”...
  • Page 6 Notes Model 9660-9660A ICB Digital Signal Processor...

  • Page 7: Introduction

    For example, a trial run com- paring the fastest available analog system, the CANBERRA 2024 Amplifier and 8715 ADC to the 9660 produced a peak resolution of 2.4 FWHM at 70 000 cps for the 9660-compared to 2.6 FWHM for the 2024/8715.
  • Page 8 All ICB NIMs feature a characteristic READY LED to indicate operational status. Software commands initiate automatic measurement of and correction for ballistic def- icit effects. 9660’s which include an “A” suffix in the model number (9660A) have the automatic pole/zero option installed. To verify the model please check the serial num- ber tag located on the NIM power connector.

  • Page 9: Controls And Connectors

    Front Panel 2. Controls and Connectors Front Panel This is a brief description of the 9660 ICB DSP’s front panel LED indicators and con- nectors. For more detailed information, refer to Appendix A, Specifications. Figure 1 Front Panel Connectors User’s Manual - ICN 9231014G...

  • Page 10: Rear Panel

    Chapter 2 - Controls and Connectors Rear Panel This is a brief description of the 9660 ICB DSP’s rear panel connectors. For more de- tailed information, refer to Appendix A, Specifications. Figure 2 Rear Panel Connectors Model 9660-9660A ICB Digital Signal Processor...

  • Page 11: Internal Controls

    SW1 is the ICB slave address switch. Select one of sixteen addresses ( 0 through 9, A through F) for the 9660. The address must be unique in any one system. The factory default is address.
  • Page 12 Chapter 2 - Controls and Connectors Digital Board Digital Board jumpers are installed at the factory to configure the 9660. If the jumpers are removed by mistake, please replace them as shown in Figure 4. W6 - jumper plug installed.

  • Page 13: Genie™ 2000 User Interface And Controls

    Defining a Detector Input The first step in using a 9660 module is to define a detector input definition at the host computer that specifies this type of device. The MCA Input Definition (MID) Editor is used for this purpose under Genie-PC and Genie-2000 (the MID Setup Wizard can also be used under Genie-2000).

  • Page 14: Mid Editor

    AIM module through the Devices/MCA menu (Figure 6). The 9660 module is thought of as three devices by the Genie-PC / Genie-2000 software: DSP Gain, DSP Filter, and Stabilizer. The ICB address of the 9660 must be defined via the Devices menu for any one of the aforementioned devices.

  • Page 15: Stabilizer Parameters

    MID Editor Stabilizer Parameters The Stabilizer settings screen (Figure 7) for the 9660 contains the following controls. Figure 7 MID Editor's Stabilizer Settings Dialog Gain Centroid Sets the centroid (in channels) of the reference peak at the high end of the spectrum for gain stabilization (Figure 8).
  • Page 16 The Zero ratio value is interpreted by the stabilizer as the ratio to maintain between the two zero windows (ratio = upper window / lower window). For instance, a value of 1 would be appropriate for a pure Gaussian peak. Model 9660-9660A ICB Digital Signal Processor...

  • Page 17: Dsp Gain Parameters

    ±10% for a sodium iodide detector. This control can only be set via the MID Editor. DSP Gain Parameters The DSP Gain settings screen (Figure 9) for the 9660 contains the following controls. Figure 9 MID Editor's DSP Gain Settings Dialog Coarse Gain Sets the device’s coarse gain.
  • Page 18 Sets the device’s conversion gain. It can be set from 256 to the maximum number of channels supported by the device. The gain will change by a factor of two. Note that this value is automatically copied down to the 9660’s internal Conversion Range pa- rameter.

  • Page 19: Dsp Filter Parameters

    (reset) input to the polarity of the preamp’s Inhibit output. This control can only be set via the MID Editor. DSP Filter Parameters The DSP Filter settings screen (Figure 10) for the 9660 contains the following con- trols. Figure 10 MID Editor's DSP Filter Settings Dialog BLR Mode Sets the baseline restorer mode.

  • Page 20: Acquisition Window Adjust Screen

    µs. Acquisition Window Adjust Screen The following section describes those parameters for the 9660 that can be accessed from the Adjust dialog screen. Note that the Adjust screen for a given device may ac- tually be composed of several screens, which are accessed by using the Next/Prev pushbuttons.
  • Page 21 Acquisition Window Adjust Screen Gain Mode Sets the Gain Stabilization mode to Off, On or Hold. Off disables gain stabilization and sets the correction adjustment to 0. On enables gain stabilization, allowing the Stabilizer to compare the incoming data to the gain Centroid and Window settings, then compensate for data below (or above) the Centroid.

  • Page 22: Dsp Gain Parameters

    (ratio = upper window / lower window). For instance, a value of 1 would be appropriate for a pure Gaussian peak. DSP Gain Parameters The DSP Gain settings screen (Figure 12) for the 9660 contains the following controls. Figure 12 Adjust Screen's Gain Settings Coarse Gain Sets the device’s coarse gain.
  • Page 23 Sets the device’s conversion gain. It can be set from 256 to the maximum number of channels supported by the device. The gain will change by a factor of two. Note that this value is automatically copied down to the 9660’s internal Conversion Range pa- rameter.

  • Page 24: Dsp Filter Parameters

    Chapter 3 - Genie™ 2000 User Interface and Controls DSP Filter Parameters The DSP Filter settings screen (Figure 13) for the 9660 contains the following con- trols. Figure 13 Adjust Screen's Filter Settings BLR mode Sets the baseline restorer mode. With a setting of AUTO, the baseline restorer is auto- matically optimized as a function of trapezoid shaping time and count rate.

  • Page 25: Genie Vms User Interface And Controls

    (GENIE-VMS 5.0 or higher) are required. Defining a Detector Input The first step in using a 9660 module is to define a detector input definition at the host computer that specifies this type of device. To do this, follow the instructions in the Model 48-0726 Genie-ESP System User’s Manual in Appendix A, under “Configuring...
  • Page 26 A description of each of the parameter settings is provided here in this chapter. In addition, a table of the suggested default values for all of the parameters is provided at the end of this section. Model 9660-9660A ICB Digital Signal Processor...

  • Page 27: Icb Dsp 9660 Setup Parameters

    PARS/GUI editor. DSP Address Sets the ICB address of the 9660 DSP module. Here you should enter the fully quali- fied address of the device, including the AIM prefix. For example, if the ICB address of the device is set to 6, and the AIM that you are using to communicate with the de- vice is NI30C, the enter NI30C:6 for the address.
  • Page 28 4096 down to correspond to channel zero of the memory). Sets the devices Lower Level Discriminator (LLD) as a percentage of the ADC’s full scale. Zero Sets the devices’ zero intercept as a percentage of the device’s full scale. Model 9660-9660A ICB Digital Signal Processor...
  • Page 29 ICB DSP 9660 Setup Parameters Conversion Gain Sets the devices’ conversion gain. It can be set from 256 to the maximum number of channels supported by the device. The gain will change by a factor of two. ADC Range Sets the devices’ ADC conversion range. It can be set from 256 to the maximum num- ber of channels supported by the device.
  • Page 30 Sets the centroid (in channels) of the reference peak at the low end of the spectrum for zero intercept stabilization. Zero Window Sets the width (in channels) of the upper and lower sampling windows on either side of the zero reference peak. Model 9660-9660A ICB Digital Signal Processor...
  • Page 31 ICB DSP 9660 Setup Parameters Zero Spacing Sets the spacing (in channels) between the upper and lower sampling windows. The windows should be placed so that a shift in the reference peak reflects a significant change in count rate through the window. For broad peaks, the spacing should be set so that the windows’...
  • Page 32 Initiates the automatic pole/zero (P/Z) process at this device. Note that you cannot per- form an Auto P/Z on a TRP type preamp. The Auto P/Z and Auto BDC processes can- not be performed simultaneously. Model 9660-9660A ICB Digital Signal Processor...

  • Page 33: 9660 Default Values

    9660 Default Values 9660 Default Values The following table shows the suggested default values for the 9660 setup parameters. These values generally serve as a good starting point. Parameter Default Value Coarse Gain Fine Gain 1.6000 Super Fine Gain 1.5003e-2...
  • Page 34 Chapter 4 - Genie VMS User Interface and Controls Zero Window Zero Spacing Zero Ratio 1.00 Gain Rate Div Zero Rate Div Gain Correction Range Zero Correction Range Zero Mode Gain Mode Preamp Type PUR Mode PUR Guard Inhibit Mode Reset Model 9660-9660A ICB Digital Signal Processor...

  • Page 35: Monitor Output

    The Monitor Output is provided as a visual aid to assist with parameter setup and ver- ify operation of the Model 9660 ICB Digital Signal Processor. The Monitor Output uses a Digital to Analog Converter (DAC) to convert or reconstruct the sampled digi- tal filtered signal (with trapezoidal weighting function) into the analog time domain for viewing.
  • Page 36 Figure 18 shows the type of waveform generated at the Monitor Output when the 9660 is connected to a detector driven by a low energy Fe source.

  • Page 37: Using The Monitor Output To Verify System Gain

    63. Using the Monitor Output to Verify System Gain The 9660 gain settings are calibrated to produce the same system gain (in keV/chan- nel) as a traditional analog system with the same settings. For a given detector, radia- tion source and MCA setup (conversion gain, conversion range, etc.), the resultant...
  • Page 38 Chapter 5 - Monitor Output The 9660 gain factor can be verified using the Monitor Output. However, keep in mind the Monitor Output signal is reconstructed in the analog time domain and is only a visual aid to assist with setup and verify operation. The Monitor Output is scaled to 8 volts full scale MCA collection as opposed to 10 volts for most traditional analog spectroscopy amplifiers.

  • Page 39: Setup And Operation

    Setting the ICB Address 6. Setup and Operation This chapter is a quick setup guide, and outlines the operation of the Model 9660 Digi- tal Signal Processor. More detailed information about specific functions can be found in Chapters 2 through 6 and the Appendices at the end of the manual. Following the procedures below will make you familiar enough with the instrument to be able to use it effectively in many situations.

  • Page 40: Icb/Mca Connections - Model 556/556A Aim

    Initialization and Self-Diagnostics When power is first applied to the Model 9660, it will go through an initialization and self diagnostics process. The BDC Busy LED on the front panel will blink for duration of the process, which requires 15 to 20 seconds to complete. The Ready LED normally remains off during the power-up process.
  • Page 41 Figure 19 Typical Gamma Spectroscopy System Perform the following steps to set up your spectroscopy system: 1. Insert the Model 9660 Digital Signal processor into a Model 2100 or equivalent NIM Bin. 2. Connect the intended Detector/Preamp to the 9660. Preamp power is provided by means of a 9-pin Amphenol connector located on the rear panel of the Model 9660.
  • Page 42 Operating Manuals of the Detector, High Voltage Power and any other accessories for specific hook up and operating instructions. 4. Turn the NIM Bin power on. At power up, the Model 9660 will go through an initialization and self-diagnostic process as described in “Initialization and Self-Diagnostics”...
  • Page 43 If the detector has a reset preamp, set Positive or Negative to match the polarity of the inhibit signal generated by the preamp. The Canberra 2101 TRP and 2008 preamps produce a positive Inhibit signal. *Coinc mode:...

  • Page 44: Detector Matching

    “0.” If using a detector with a Reset preamp such as the Canberra 2101 or 2008, change the preamp type from RC to TRP. With TRP selected, the Pole/Zero compensation is au- tomatically set to a value of “0"...
  • Page 45 Detector Matching The Automatic Pole/Zero (P/Z) feature will give good results for most detector appli- cations and count rates. However, it may be necessary to optimize the P/Z compensa- tion manually at extremely high count rates or for specific applications where the digitally filtered trapezoid signal is prevented from returning monotonically to the baseline.
  • Page 46 (ICR) exceeds 20 kHz. The Auto Pole/Zero will not converge properly if the ICR exceeds 20 kHz. For this condition, the error message will be posted very quickly; long before the two minute time out. Model 9660-9660A ICB Digital Signal Processor...

  • Page 47: Manual Pole/Zero Matching

    Trapezoid signal as it returns to the baseline, it should return with no over or undershoot. Set the oscilloscope vertical range to an appropriate sensitivity. Use a Canberra Schottky Clamp Box, Model 1502 or equivalent to prevent oscilloscope overload.
  • Page 48 Figure 20 Pole/Zero Compensation - Examples To prevent scope overload and increase the P/Z matching accuracy, a clamping circuit such as the Canberra Model LB1502 Schottky Clamp Box should be connected at the scope input. P/Z Matching Using a Ge Detector and 1.
  • Page 49 Detector Matching preamp matching misadjustment, which exhibit a much longer time constant and have a larger performance impact. At high count rates, P/Z matching misadjustment will affect spectral peak shape and resolution. Scope: Vertical: 50 mV/div Horizontal: 10 µs/div Source: 1.33 MeV peak at 6 V amplitude Count rate: 2kcps Shaping: 5.6 µs rise time...

  • Page 50: Automatic Ballistic Deficit Correction

    The Trapezoidal shaping function employed in the 9660 allows independent adjustment of the Rise/Fall time and Flat Top. The Rise/Fall time sets the noise filtering characteristics and the Flat Top adds sufficient time for the charge to be collected and integrated.
  • Page 51 Detector Matching Optimizing the Flat Top on the 9660 is automatic and easy; manual adjustment is not necessary. Automatic adjustment of the Flat Top time is performed by initiating the Auto BDC (ballistic Deficit Correction) function. A sophisticated algorithm measures the detector pulses, determines the range of detector rise times, and sets the digital fil- ter trapezoid flat top for full charge integration.

  • Page 52: Spectroscopy Operation

    Place a low activity Co source on the detector. Set the MCA to COLLECT or ACQUIRE. For the 9660 setup performed in “Spectroscopy System Setup” on page 34, the 1332 keV Co peak should collect in channel 6500 to 7200 for a detector preamp gain of 500 mV/MeV and 8192 memory or spectrum size.

  • Page 53: Pur/Ltc Operation

    Pileup Rejection With a Live Source 7. PUR/LTC Operation The Model 9660 ICB Digital Signal Processor includes a pileup rejector and live time corrector. The pile up rejector inspects for pulse pileup and allows only non-piled up events to be processed and stored into the spectrum. The result is a reduced number of counts in the pileup region and reduced spectral interference for improved quantitative measurement and analysis.
  • Page 54 If for some reason readjustment is necessary, please follow the directions “Detector Matching” on page 38. Adjust the 9660 Gain to locate the 122 keV Co peak in channel 3500. This is to allow the Pileup region and sum peaks to be viewed in the upper half of the spectrum.

  • Page 55: Live Time Correction With A Live Source

    Fast Discriminator (fast channel) and the pulse evolution time or dead time of the shaped signal (slow channel). In the case of the 9660 DSP, the slow channel is the dig- ital filtered trapezoid signal. Accurate Live Time Correction is obtained when the en- ergy threshold and dynamic range of the fast channel and slow channel are the same.
  • Page 56 Chapter 7 - PUR/LTC Operation On the 9660 DSP, the “LT Trim” function allows minor adjustment of the pulse evolu- tion time or dead time of the digital trapezoid signal to normalize the fast and slow channel energy thresholds without affecting the spectral low energy cutoff threshold.

  • Page 57: Pur Guard

    PUR Guard 8. Clear the MCA, Collect a new spectrum for 500 live seconds, and record the net area of source the 1173.2 keV Co reference peak. 9. Compare the net area of the 1173.2 keV Co peak acquired in step 6 and compute the percentage change.
  • Page 58 PUR Guard should be increased as shown. Some detectors with RC preamps may exhibit secondary time constants which is evi- dent by a short lived undershoot or ring on the trailing edge of the shaped signal (see Figure 26). Model 9660-9660A ICB Digital Signal Processor...

  • Page 59: Pur Guard Setup

    PUR Guard Scope: Vertical: 10 µs/div Horizontal 20 mv/div Figure 26 Preamplifier Secondary Time Constant This behavior is usually due to non-ideal characteristics of the preamp feedback resis- tor. Events that fall on the tail of an event which exhibits this behavior will become corrupted or distorted when minimal guard time is selected.

  • Page 60: Pur Guard Adjustment Using A Live Spectrum

    PUR Guard time to the next higher setting. Live Time Correction Using the LFC Module The Model 9660 Digital Signal processor can be used with the Model 599 Loss Free Counting Module (LFC). The 599 LFC provides the ability of correcting for counting losses as they occur in real time, rather than extending the measurement duration as in conventional live time correction.

  • Page 61: Lfc System Setup

    Connect the 9660 DSP, 599 LFC and 556/556A AIM as shown in Figure 27. Figure 27 LFC System Setup On the MCA Adjust Screen, set the LTC Mode on the 9660 DSP to LFC; this will enable Loss Free Counting. The LTC Mode selection is located on the Gain Device Adjust Screen.

  • Page 62: Specifications

    Dead Time signal for the duration of the INH signal; RESET preamp se- lected: inhibits the 9660 during the preamplifier reset cycle, the leading edge of the INH signal resets the pileup rejector and initiates the 9660 to automatically disable pulse processing and extend the system dead time for the duration of the resultant overload event.

  • Page 63: Front Panel Indicators

    ≈ 50 Ω; rear panel BNC connector. DATA - Provides 14 binary TTL-compatible output lines and the data transfer com- mands required for MCA interface; data interface is compatible with the Canberra Model 556/556A Acquisition Interface Module (AIM), rear panel 34-pin ribbon cable connector.
  • Page 64 Inp Polarity - Selects either POSITIVE or NEGATIVE input polarity. Inhibit Mode - Selects either NORM or RESET inhibit modes; with NORM selected, the system is gated off while external INHIBIT is set true. In RESET Model 9660-9660A ICB Digital Signal Processor...
  • Page 65 ICB Programmable Controls mode, the inhibit time is automatically extended to account for the system overload recovery time or while external INHIBIT is set true. Coinc Mode - Selects either COINCidence or ANTIcoincidence gating. In the COINCidence mode (ANTIcoincidence) a positive GATE pulse enables (disables) the conversion of the present input.

  • Page 66: Performance

    +24 V dc – 90 mA +12 V dc – 200 mA +6 V dc – 1.5 A –24 V dc – 90 mA –12 V dc – 150 mA –6 V dc – 1.2 A Model 9660-9660A ICB Digital Signal Processor...

  • Page 67: Connectors

    Connectors Connectors With the exception of the NIM BIN and preamp power connectors, all signal connec- tors are BNC type. Preamp Power - Rear panel, Amphenol, type 17-10070. Data - Rear panel, 34 pin ribbon ICB - Rear panel, 20 pin ribbon. Cables A 12 port ICB connecting cable and 34 pin data cable are supplied with each Model 556/556A AIM.

  • Page 68: Ordering Information

    Appendix A - Specifications Ordering Information 9660 - ICB programmable Digital Signal processor 9660A - ICB programmable Digital Signal Processor with automatic pole/zero option installed. Model 9660-9660A ICB Digital Signal Processor...

  • Page 69: Performance Adjustments

    This appendix describes how to make several performance adjustments: adjusting the rise time and the flat top, matching the pole/zero manually, setting the baseline re- storer, setting the fast discriminator threshold, and operating the 9660 with reset preamps. Rise Time and Flat Top Adjustments The digital filter employed in the 9660 has a Triangular/Trapezoidal weighting or shaping function.
  • Page 70 Gaussian shaping. Table B.1 lists the 9660 Rise Time and Flat Top settings which optimize performance for high throughput/good resolution and optional setting for best resolution/lower throughput when using Germanium Coaxial detectors.
  • Page 71 Settings for typical germanium coaxial detectors have been discussed above. Table B.2 lists 9660 rise time and flat top settings for other common detectors. Table B.2 Settings for Other Common Detectors...

  • Page 72: Pole/Zero Matching - Supplementary Information

    Appendix B - Performance Adjustments Flat Top Setting The 9660 allows independent selection of rise time and flat top. A detector with long charge collection times will require a flat top long enough to process all the charge from the detector (see “Automatic Ballistic Deficit Correction” on page 44). If the flat...
  • Page 73 Pole/Zero Matching - Supplementary Information triggering so that the positive trapezoid output is observed, then set the square wave generator’s amplitude control (attenuator) for an amplitude of 6 Change the scope vertical sensitivity to 50 mV/div. To prevent scope overload, clamp the Monitor output signal by moving the LB1502 Clamp Box switch to the CLAMP position.

  • Page 74: Pole/Zero Matching And "Wrap Around

    Often a clamp box such as the LB1502 can still be used to make the pole zero adjustment (see Figure 31, where the gain has been ad- justed to produce “wrap around”). Model 9660-9660A ICB Digital Signal Processor...
  • Page 75 Pole/Zero Matching - Supplementary Information Scope: Vertical: 50 mV/div Horizontal: 10 µs/div Source: Count rate: 2 kcps Shaping: 5.6 µs rise time 0.8 µs flat top Figure 31 Undercompensated Pole/Zero with Wrap Around However if the signal is very noisy, the noise may exceed the range of the clamp box and the pole zero adjustment should be made by viewing the monitor output directly (see Figures 32, 33 and 34).
  • Page 76 Figure 33 Correct Pole/Zero Comp with Noisy Detector Scope: Vertical: 500 mV/div Horizontal: 50 µs/div Source: Count rate: 2 kcps Shaping: 8 µs rise time 2.4 µs flat top Figure 34 Overcompensated Pole/Zero with Noisy Detector Model 9660-9660A ICB Digital Signal Processor...

  • Page 77: Baseline Restorer

    “wrap around,” while maintaining good signal/noise conditions for adjusting the pole zero. When completed, return the 9660 gain to the setting required for the intended ap- plication. If a high energy source is not available, the “wrap around” can still be de- creased by simply lowering the gain or rise time setting.

  • Page 78: Manual Fast Discriminator Threshold

    Operation with Reset Preamps and Selecting Inhibit Mode The 9660 Digital Signal processor is fully compatible with most pulsed reset preamplifiers. Reset preamps use an electronic circuit, as opposed to a feedback resis- tor, to restore the preamp back to a reference level. As a result, the preamp output is a succession of step functions that staircase or ramp up to an upper limit or threshold that initiates a preamp reset.

  • Page 79: Pole/Zero Setting For Reset Preamps

    Pole/Zero compensation is not required. For this appli- cation, the Pole/Zero should be set off or to infinity. On the 9660, this is accomplished by setting the preamp type to RESET. The preamp type can be changed in the Filter Device MID Editor.
  • Page 80 Using a “Tee” connector, connect the preamp’s Inhibit signal to the INHIBIT BNC connector located on the rear panel of the 9660. Monitor the preamp’s Inhibit signal and the 9660s Trapezoid signal, viewed on the Monitor Output, using an oscilloscope.
  • Page 81 Figure 36 Setting Reset Preamp Inhibit Pulse Width The 9660’s overload recovery time is approximately 40 µs with the Rise time set to 5.6 µs and Flat Top set to 0.8 µs and using a Canberra Model 2101 preamp and source. User’s Manual - ICN 9231014G...

  • Page 82: Data And Icb Interface Connectors

    MCA or CPU. Due to a two-deep data buffer, the 9660 can begin processing the next event even though data transfer to the memory unit is still in process.

  • Page 83: Data Connector

    Data Connector Data Connector This 34-pin ribbon connector (J102) provides all the necessary signals for connection to the MCA. Negative true signals are shown with a trailing asterisk (ACEPT*); all other signals are positive true. Figure 38 Representative Interfacing Logic Figure 39 Data Transfer Timing Diagram User’s Manual - ICN 9231014G...
  • Page 84 All input and output signals are considered to be a logic 1 for a high voltage level unless the signal name is followed by an asterisk (*), in which case the signal is considered to be a low voltage level. SIGNAL DESCRIPTION ADC0* OUTPUT: Binary data 2 (LSB) Model 9660-9660A ICB Digital Signal Processor...
  • Page 85 MCA menu. CDT* or OUTPUT (Composite Dead Time): This signal indicates the time when the 9660 is busy and cannot accept another input event. Enable/Dis- able polarity is programmed with selection of MCA type through the MCA menu.

  • Page 86: Icb Connector

    (LWE*), in which case the signal is consid- ered to be a logic 1 for a low voltage level. The direction of the signal is referenced to the amplifier. Model 9660-9660A ICB Digital Signal Processor...
  • Page 87 ICB Connector Signal Direction Description Input/Output Address/Data line 0 (LSB) Input/Output Address/Data line 1 Input/Output Address/Data line 2 Input/Output Address/Data line 3 Input/Output Address/Data line 4 Input/Output Address/Data line 5 Input/Output Address/Data line 6 Input/Output Address/Data line 7 (Write Enable) This signal is LWE* Input active when the ICB Master is...

  • Page 88: Installation Considerations

    • Compliant grounding and safety precautions for any internal power distribution • The use of CE compliant accessories such as fans, UPS, etc. Any repairs or maintenance should be performed by a qualified Canberra service representative. Failure to use exact replacement components, or failure to reassemble the unit as delivered, may affect the unit’s compliance to the specified EU...
  • Page 89 Canberra (we, us, our) warrants to the customer (you, your) that for a period of ninety (90) days from the date of shipment, software provided by us in connection with equipment manufactured by us shall operate in accordance with applicable specifications when used with equipment manufactured by us and that the media on which the software is provided shall be free from defects.

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