Pin Description; Gal16Lv8; Description - Hitachi 42PD3200A Service Manual

12.7.3. Pin Description

DS90C385 MTD56 (TSSOP) Package Pin Description-FPD Link Transmitter
Pin Name I/O No.
I 28
TxIN
O 4
TxOUT+
TxOUT- O 4
I 1
TxCLKIN
I 1
R_FB
O 1
TxCLK OUT+
O 1
TxCLK OUT-
I 1
PWR DOWN
I 3
Vcc
I 4
GND
I 1
PLL Vcc
I 2
PLL GND
I 1
LVDS Vcc
LVDS GND I 3
DS90C385SLC SLC64A Package Pin Description-FPD Link Transmitter
Pin Name I/O
I
TxIN
O
TxOUT+
TxOUT- O
I
TxCLKIN
I
R_FB
O
TxCLK OUT+
O
TxCLK OUT-
I
PWR DOWN
I
Vcc
I
GND
I
PLL Vcc
I
PLL GND
I
LVDS Vcc
LVDS GND I
NC
12.8.

GAL16LV8

12.8.1. Description

The GAL16LV8D, at 3.5ns maximum propagation delay time, provides the highest speed performance
available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5Vsignal levels. The
GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E
combines CMOS with Electrically Erasable (E
(<100ms) allow the devices to be reprogrammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and
supports all architectural features such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during
manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality
of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are
specified.
Description
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines —FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differentiaI data output.
Negative LVDS differential data output.
TTL Ievel clock input. Pin name TxCLK IN.
Programmable strobe select
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at
power down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
No. Description
TTL level input.
28
4 Positive LVDS differentiaI data output.
4 Negative LVDS differential data output.
TTL Ievel clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
1
1
Programmable strobe select. HIGH = rising edge, LOW = falling edge.
1 Positive LVDS differential clock output.
1
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low
1
current at power down.
3 Power supply pins for TTL inputs.
5 Ground pins for TTL inputs.
1
Power supply pin for PLL.
Ground pins for PLL.
2
2 Power supply pin for LVDS outputs.
4 Ground pins for LVDS outputs.
6
Pins not connected.
2
) floating gate technology. High speed erase times
14
2
CMOS process, which