Diagrams - Sony DR-BT22 Service Manual
Wireless stereo headset
Hide thumbs
Also See for DR-BT22:
- Operating instructions manual (56 pages) ,
- Specifications (1 page) ,
- Operating instructions manual (56 pages)
Table of Contents
Advertisement
THIS NOTE IS COMMON FOR PRINTED WIRING BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is printed in each block.)
for schematic diagram:
Note:
• All capacitors are in µF unless otherwise noted. (p: pF)
50 WV or less are not indicated except for electrolytics
and tantalums.
1
• All resistors are in Ω and
/
W or less unless otherwise
4
specified.
•
%
: indicates tolerance.
• C : panel designation.
• A : B+ Line.
• Power voltage are dc 3.7 V and fed with regulated dc
power supply from battery terminal.
• Voltages are dc with respect to ground under tolerances.
no mark : STANDBY
(
) : AC ADAPTOR IN
• Voltages are taken with a VOM (Input impedance 10 MΩ).
Voltage variations may be noted due to normal production
tolerances.
• Signal path.
F
: AUDIO
• IC101 (CXN1450-2ABL) on MAIN board cannot be
replaced individually.
Replace it with "MAIN BOARD, COMPLETE".
• The voltage of IC101 cannot be measured.
DR-BT22
SECTION 3
DIAGRAMS
for printed wiring boards:
Note:
• X : parts extracted from the component side.
• Y : parts extracted from the conductor side.
•
: Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
Caution:
Parts face side:
Parts on the parts face side seen from the
(Side A)
parts face are indicated.
Pattern face side:Parts on the pattern face side seen from
(Side B)
the pattern face are indicated.
• MAIN board is four-layer pritnted board.However, the
patterns of layer 2 and 3 have not been included in this
diagrams.
• IC Block Diagrams
— CHARGER Board —
IC251 XC9103D093MR
CURRENT
FB
1
RIPPLE DETECT
AND FB
+
VDD
2
VDD
–
ERROR AMP
VREF WITH
SOFT START,
CE
CE
3
IC261 BQ24010ADRCR
IN
1
V
I(BAT)
V
O(REG)
CHG ENABLE
VCC
2
VCC
REFERENCE
VCC
AND BIAS
V
I(BAT)
V
(SLP)
STAT1
3
STAT2
4
V
O(REG)
V
I(BAT)
V
(RCH)
V
I(BAT)
VSET
V
I(SET)
V
(PRECHG)
V
(TAPER)
V
I(SET)
V
(TERM)
5
VSS
7
7
PHASE
VDD
COMPENSATION
PWM
COMPARATOR
+
BAFFER,
DRIVER
–
RAMP WAVE
PWM/PFM
GENERATOR,
CONTROLER
OSC
V
(ISET)
I
I
(DETECT)
(FAULT)
V
ENABLE
ENABLE
VSET
CHG ENABLE
V
O(REG)
THERMAL
SHUTDOWN
DEGLITCH
CHARGE
CONTROL,
TIMER,
AND
DISPLAY
LOGIC
I
ENABLE
RECHARGE
(FAULT)
DEGLITCH
I
ENABLE
PRECHARGE
(DETECT)
CHG ENABLE
TAPER
DEGLITCH
TERM
DEGLITCH
DR-BT22
5
EXT
4
GND
10
OUT
9
BAT
I(BAT)
VCC
8
TS
PG
7
PG
6
ISET
Advertisement
Table of Contents
