Table of Contents
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Parameter
Target Static Lane Select
Upper 32 bits
Target Static Lane Select
Lower 32 bits
Target Static Lane Select
ECC
Target Static Lane Value
Worst Case Margin
Granularity
Read Voltage Sweep Step
Size
Read Timing Sweep Step
Size
Write Voltage Sweep Step
Write Timing Sweep Step
Size
Silent Execution
Description
This item is configurable when Target Static Lane Control is set to
Enabled.
This item is configurable when Target Static Lane Control is set to
Enabled.
This item is configurable when Target Static Lane Control is set to
Enabled.
This item is configurable when Target Static Lane Control is set to
Enabled.
Configures Worst Case Margin Granularity.
Options available: Per Chip Select, Per Nibble.
Default setting is Worst Case Margin Only.
Configures the step size for read Data Eye voltage sweep.
Options available: 1, 2, 4. Default setting is 2.
Configures the step size for read Data Eye timing sweep.
Options available: 1, 2, 4. Default setting is 1.
Configures the step size for write Data Eye voltage sweep.
Options available: 1, 2, 4. Default setting is 2.
Configures the step size for write Data Eye timing sweep.
Options available: 1, 2, 4. Default setting is 1.
Enable Mbist Target Static Lane Control.
Options available: Enabled, Disabled. Default setting is Disabled.
BIOS Setup
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