CAES SPARC V8 User Manual

SPARC V8 Processor
LEON-XCKU-EX
Features
SPARC V8e integer
• unit(s)
with dual-issue pipeline,
16 KiB instruction and
16 KiB data caches,
hardware multiplier and
divider, power-down mode,
hardware watchpoints, etc.
• Double precision IEEE-754 floating point unit
• Memory management unit
• Advanced on-chip debug support unit
• Level-2 cache
• DDR4 SDRAM
• UART, Timers, GPIO port, Interrupt controller,
Status registers
• Ethernet 10/100/1000 Mbit MAC interface
Applications
The LEON/GRLIB template designs can be adapted as multiple configurations,
covering instrument, payload and control applications.
LEON-XCKU-EX-UM
Jan 2022, Version 1.1
Description
The LEON-XCKU FPGA bitstreams are a collection of
example designs built from Cobham Gaisler's GRLIB
IP library using a template design for Xilinx Kintex
Ultrascale devices. The example designs are suit-
able for evaluation of LEON microprocessors in sys-
tem-on-chip designs.
Specification
• Targets Xilinx Kintex Ultrascale KCU105 Evalua-
tion Kit FPGA board
• 100 MHz system frequency
Kungsgatan | SE-411 19 | Goteborg | Sweden
+46 31 7758650 | www.caes.com/gaisler
Cobham Gaisler AB