CAES RISC-V NOEL-ARTYA7-EX User Manual

RISC-V Processor
NOEL-ARTYA7-EX
NOEL-ARTYA7-EX Features
RISC-V
• NOEL-V processor with 64-bit architec-
ture 16 KiB instruction and 16 KiB data caches,
memory management unit, hardware multiplier
and divider, in single and multi-core configura-
tions
• RISC-V standard Platform-Level Interrupt Con-
troller
• RISC-V standard PMP
• RISC-V standard debug support
• Level-2 cache
• DDR4 SDRAM
• UART, Timers, GPIO port, Status registers
• Ethernet 10/100 Mbit MAC interface
The NOEL/GRLIB template designs can be adapted as multiple configurations,
covering instrument, payload and control applications.
NOEL-ARTYA7-EX-UM
Jul 2022, Version 2.0
Description
The NOEL-ARTYA7 FPGA bitstreams are a collection
of example designs built from Cobham Gaisler's
GRLIB IP library using a template design for Xilinx
Artix-7devices. The example designs are suitable for
evaluation of NOEL microprocessors in system-on-
chip designs.
Specification
• Targets Arty A7: Artix-7 FPGA Development
Board (A7-100T version)
Applications
Kungsgatan | SE-411 19 | Goteborg | Sweden
+46 31 7758650 | www.caes.com/gaisler
Cobham Gaisler AB