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Tern P52 Technical Manual

I/o expansion card with adc, dac, 24 ppi i/os, 100m baset ethernet, quadrature decoders, rs232/485
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P52
™
I/O expansion card with ADC, DAC, 24 PPI I/Os, 100M BaseT Ethernet,
Quadrature Decoders, RS232/485
Technical Manual
1724 Picasso Avenue, Davis, CA 95616, USA
Tel: 530-758-0180
Fax: 530-758-0181
Internet Email: sales@tern.com
http://www.tern.com

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Summary of Contents for Tern P52

  • Page 1 ™ I/O expansion card with ADC, DAC, 24 PPI I/Os, 100M BaseT Ethernet, Quadrature Decoders, RS232/485 Technical Manual 1724 Picasso Avenue, Davis, CA 95616, USA Tel: 530-758-0180 Fax: 530-758-0181 Internet Email: sales@tern.com http://www.tern.com...

  • Page 2: Important Notice

    TERN and the Buyer agree that TERN will not be liable for incidental or consequential damages arising from the use of TERN products. It is the Buyer's responsibility to protect life and property against incidental failure.

  • Page 3: Chapter 1: Introduction

    1.1 Functional Description Measuring 4.4 x 3.1 inches, the P52 is an I/O expansion board designed for and driven by a Tern host controller. A 16-bit external data bus is required to run the parallel ADC and DAC on the P52. Many embedded applications demand high speed ADC and DAC with buffered operational amplifiers supporting variable gains or offset for analog signals.
  • Page 4 Two channels of RS-232 drivers and a 5V linear regulator are on-board. An optional RS232 or RS485 driver can be installed for the optional 3 UART of the host controller. The P52 requires 8.5V to 12V DC power supply with linear regulator, or up to 30V DC power input with an optional switching regulator without generating excessive heat.

  • Page 5: Chapter 2: Installation

    SER0 for debugging by default. Thus, the 5x2 IDC connector must be installed on the SER0 of the P52 (header H2). IMPORTANT: Note that the red side of the cable must point to pin 1 of the H2 header. The DB9 connector should be connected to one of your PC's COM Ports (COM1 or COM2).
  • Page 6 P52 header H2 (Ser 0) will be blocked off. To negotiate with this change, we can use the debug port (Ser 0) on the host controller and avoid Serial ports 0 and 1 on the P52, as shown below with the 5P as host.

  • Page 7: Chapter 3: Hardware

    3.1 Engine controllers The P52 was designed to be driven by a Tern host controller, using the 16-bit external data/address bus to drive the parallel ADC and DAC, as well as other components. Any ‘Engine’ used will be installed on top of the P52 via 20x2 pin headers J1 and J2, and can be secured by two #4-40 mounting screws.
  • Page 8 Chapter 3: Hardware 3.3 I/O Mapped Devices 3.3.1 I/O Space External I/O devices can use I/O mapping for access. You can access such I/O devices with inportb(port) or outportb(port,dat). These functions will transfer one byte of data to the specified I/O address. Refer to the software chapter of the controlling Engine’s technical manual for additional information on I/O space and access.
  • Page 9 S e l e c t Figure 3.1 Mode Select Command Word P52 maps U1, the PPI 8255, at base I/O address PPI = 0x1080 (586-Engine) and 0x00 (186-Engine). All ports/registers are offsets of this I/O base address. The Command Register address = PPI+6; Port 0 address = PPI+0; Port 1 address = PPI+2;...
  • Page 10 The DAC requires an external 5V reference given by a precision reference installed at U0. The P52 uses data bus D15 to D0 to directly interface to the DAC’s full 16-bit data bus for maximum data transfer rate. Four outputs are routed to J5.17-20.
  • Page 11 Ethernet connectivity. 3.3.7 Opto-couplers There are 8 opto-couplers on the P52. These opto-couplers provide optical isolation and can be used for digital inputs, relay contact monitor, or powerline monitor. These optos have a 3 micro-second ON time and 5 micro-second OFF time.

  • Page 12: Headers And Connectors

    Chapter 3: Hardware 3.4 Headers and Connectors Two 20x2, 0.1 spacing sockets are installed on the P52. H2 pin 1 H3 pin 1 H4 pin 1 J3 pin 1 J1 pin 1 H7 pin 1 H0 pin 1 H8 pin 1...
  • Page 13 3.4.2 Expansion Headers J1 and J2 J2 Signal J1 Signal TXD0 /INT RXD0 /RTS1 VOFF TXD1 RXD1 /RST /CTS1 /CS6 Table 3.1 J1 and J2, 20x2 expansion ports for P52 Signal definitions for J1: +5V power supply Ground Software programmable clock output from host...
  • Page 14 Chapter 3: Hardware data receive of UART SCC2691 data transmit of UART SCC2691 Multi-Purpose Output of SCC2691 VOFF real-time clock output D0-D15 external data bus A7-A0 lower address lines /RST reset signal, active low reset signal, active high /CS6 8-bit chip select on the host active low when write operation active low when read operation Signal definitions for J2:...

  • Page 15: Appendix A: P52 Mechanical Dimensions

    Appendix A: P52 mechanical dimensions ___________________________________________________________________________________ Appendix A: P52 mechanical dimensions 2.18, 2.99 3.08, 2.99 3.37, 2,49 4.43, 3.08 0.13, 2.73 4.31, 2.73 SER0 HC14 HC14 10BT U2 CS89 4.33, 2.03 SER1 0.33, 2.53 U1 PPI 4.33, 1.28 U3 DAC 0.17, 0.59...
  • Page 16 IMPUL IMPUL /RXD1 RXD1 TXD1 /TXD0 TXD0 /RXD0 RXD0 MAX232A AD7655 DA8544 AD7655 AD7655 AD7655 VCC R4 CHB1 CHB2 P52-P000.PDS R0 2K CHA1 CHA2 /RTS1 /TXD IDX1 IDX2 /CTS1 /RXD LM285 VCC R6 /CS6 CAPNP /PPI MAX232A /CS6 /ADR /AD1...

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