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Tern V104 Technical Manual

C/c++ programmable 16-bit microprocessor module based on the nec v25, with a pc/104 bus
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V104
™
C/C++ Programmable 16-bit Microprocessor Module
Based on the NEC V25, with a PC/104 Bus
Technical Manual
th
1950 5
Street, Davis, CA 95616, USA
Tel: 530-758-0180
Fax: 530-758-0181
Email:
sales@tern.com
http://www.tern.com

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  • Page 1 V104 ™ C/C++ Programmable 16-bit Microprocessor Module Based on the NEC V25, with a PC/104 Bus Technical Manual 1950 5 Street, Davis, CA 95616, USA Tel: 530-758-0180 Fax: 530-758-0181 Email: sales@tern.com http://www.tern.com...
  • Page 2 TERN and the Buyer agree that TERN will not be liable for incidental or consequential damages arising from the use of TERN products. It is the Buyer's responsibility to protect life and property against incidental failure.

  • Page 3: Chapter 1: Introduction

    It is designed for embedded applications that require compactness, low power consumption, and high reliability. The V104 can be integrated into an OEM product as a processor core component. It also can be used to build a smart sensor, or as a node in a distributed microprocessor system.

  • Page 4: Standard Features

    A 16-pin LCD interface header supports various types of LCD modules. By default, the LCD select line is active high. The optional VE232 provides regulated 5V power and RS232/RS485 drivers for the V104. The V104 can also be installed on the A-Drive to provide regulated 5V power and RS232/RS485 drivers. TERN also offers custom hardware and software design, based on the V104 or other TERN controllers.

  • Page 5: Physical Description

    Replace Debug ROM, project is complete. You can program the V104 from your PC via serial link with an RS232 interface. Your C/C++ program can be remotely debugged over the serial link at a rate of 115,000 baud. The C/C++ Evaluation Kit (EV) or...
  • Page 6 After you debug your program, you can test run the V104 in the field, away from the PC, by changing a single jumper, with the application program residing in the battery-backed SRAM. When the field test is complete, application ROMs can be produced to replace the DEBUG ROM.
  • Page 7 • If a jumper is on J10 pins 19-20 at power-on or reset, the V104 will operate in Step Two mode. If the jumper is off J10 pins 19-20 at power-on or reset, the V104 will operate in Step One mode. The status of J10 pin 19 (signal P02 of the NEC V25) is only checked at power-on or at reset.

  • Page 8: Minimum Hardware Requirements

    The C/C++ Evaluation Kit (EV) and C/C++ Development Kit (DV) are available from TERN. The EV Kit is a limited-functionality version of the DV Kit. With the EV Kit, you can program and debug the V104 in Step One and Step Two, but you cannot run Step Three. In order to generate an application ROM/Flash file,...

  • Page 9: Chapter 2: Installation

    Hardware installation for the V104 consists primarily of connecting the microcontroller to your PC. For the V104, the VE232 must be used to supply regulated power and RS232 drivers to the V104. If you are using the V104 installed on another controller, please refer to the technical manual for that controller for installation information.
  • Page 10 Install the VE232 interface with the H1 (10x2) socket connector on the upper half of the J2 (dual row header) of the V104. Figure 2.1 and Figure 2.2 show the VE232 and the V104 before and after installation. 2.2.2 Connecting the V104 to the PC The following diagram (Figure 2.3) illustrates the connection between the V104, VE232, and the PC.
  • Page 11 Chapter 2: Installation 2.2.3 Powering-on the V104 Connect a wall transformer +9V DC output to the VE232 DC power jack. The on-board LED should blink twice and remain on after the V104 is powered-on or reset (Figure 2.4). PC/104 Bus V25 CPU VE232 Figure 2.4 The LED blinks twice after the V104 is powered-on or reset...

  • Page 12: Chapter 3: Hardware

    2) program PM0 register and set PM0 bit 5=0, which defines P05 as output. 3) Write a “1” to P0 data register bit 5, the P05 pin on the V104 J2-5 should be high (5V). Write a “0” to P0 data register bit 5, the P05 pin on the V104 J2-5 should be low (0V).
  • Page 13 Chapter 3: Hardware V104 INPUT J10 pin 9. INPUT J10 pin 8. PT7* INPUT J10 pin 7. P00, P01, P05, P07, P17, P24-27 are used by system and ADC. While using the DEBUG EPROM, P02 is used to select STEP 1 (DEBUG mode) or STEP 2 (standalone mode) during the power on or reset, see Fig 1.2a for detail.
  • Page 14 (Figure 3.1). The PFI pin has been pulled high to VCC with a 10K resistor on the V104. When the external DC power drops and the voltage on the PFI (J2 pin 8) is less than 1.3 V, the MAX691 will pull down PFO pin, and NMI will occur.
  • Page 15 For SER0 and SER1, a built-in baud rate generator can be used to select standard baud rates from 110 to 1.25 M. One of these internal serial ports is used by the V104 for programming with the PC. It uses 115,000 Baud rate for programming.
  • Page 16 M o d e S e l e c t Figure 3.2 Mode Select Command Word The V104 maps U11, the 82C55/uPD71055, in I/O space to 0xC100 to 0xC103. The Command Register = 0xC103. Port 0 = 0xC100. Port 1 = 0xC101.

  • Page 17: Other Devices

    RTS and CTS mechanism. For more information, refer to Appendix C. The SCC2691 on the V104 may be used as a network 9th-bit UART. The RxD and TxD signals are routed to the J2 header for connecting to a VE232. Use J1 pin 3 (RS485-) and pin 4 (RS485+) on the VE232 to join the multi-drop RS485 twist pair network.
  • Page 18 The V104 uses P03 to hit the watchdog timer via J7 1-2. Watchdog Timer The watchdog timer is activated by setting a jumper on J7 pins 1-2 of the V104. The watchdog timer provides a means of verifying proper software execution. In the user's application program, calls to the function hitwd() (a routine that toggles the P03=HWD pin of the MAX691) should be arranged such that the HWD pin is accessed at least once every 1.6 seconds.

  • Page 19: Jumpers And Headers

    16 pin chip. The MAX537 operates with ±5V power supply. Each DAC has a double- buffered input. A 16-bit serial word is used to load data into input/DAC register. The V104 uses P20=/LD, P21=DAC /CS, P24=SCLK, and P25=SDI to operate the MAX537. The REF+ of the MAX537 is 2.5V provided by U14.
  • Page 20 V104 Chapter 3: Hardware pin 1=2 Enable watchdog timer. pin 3=4, Enable EEPROM write protection, pin 4=5 no write protection Reset. SCC2691 MPO and MPI LCD interface UART SCC2691 MPO and MPI...

  • Page 21: Chapter 4: Software

    Implicit accesses to I/O and memory address space occur throughout your program from TERN libraries as well as simple memory accesses to either code or global and stack data. You can, however, explicitly access any address in I/O or memory space, and you will probably need to do so in order to access processor registers and on-board peripheral components (which often reside in I/O space) or non-mapped memory.
  • Page 22 This function can be used to retrieve data from components in I/O space. You will find that most hardware options added to TERN controllers are mapped into I/O space, since memory space is valuable and is reserved for uses related to the code and data. Using I/O mappings, the address is output over the address bus, and the returned 16 or 8-bit value is the return value.
  • Page 23 4.2.1 V104 Initialization VE_init This function should be called at the beginning of every program running on V104 core controllers. It provides default initialization and configuration of the various I/O pins, interrupt vectors, sets up expanded DOS I/O, and provides other processor-specific updates needed at the beginning of every program.
  • Page 24 4.2.3 I/O Initialization There are two ports of 16 I/O pins available on the V104. Hardware details regarding these PIO lines can be found in the Hardware chapter. There are several functions provided for access to the PIO lines. At the beginning of any application where you choose to use the PIO pins as input/output, you will probably need to initialize these pins in one of the four available modes.
  • Page 25 Set port 0 as I/O, bits 0 – 3 as input, 4 – 7 as output. Example 4.1 port_init(0, 0x00, 0xf0); p = Port 0, pmc = 0 (I/O), pm 0-3 = 1, pm 4-7 = 0. Set pins 20 and 23 as DMA Request. All other port 2 pins as output. Example 4.2 port_init(2, 0x09, 0x00);...
  • Page 26 /* assume pm2 has been correctly maintained. The following code will modify the pm2 register such that bits 0 through 3 are low. Use AND to set bits low */ pokeb(0xfff0, 0x11, ( pm2 = ( pm2 & 0xF0 ) ) ); //pm2 must be set to a new register value Example 4.6 Set port 2 pins 0 through 3 as input.
  • Page 27 4.2.5 Timer Units The two timers present on the V104 can be used for a variety of applications. The timers run at a maximum of 1/6 of the processor clock rate, which determines the maximum resolution that can be obtained.
  • Page 28 Real-Time Clock The real-time clock can be used to keep track of real time. Backed up by a lithium-coin battery, the real time clock can be accessed and programmed using two interface functions. The real time clock only allows storage of two digits of the year code, as reflected below. As a result, application developers should be careful to account for a roll-over in digits in the year 2000.
  • Page 29 The internal asynchronous serial ports are functionally identical. SER0 is used by the DEBUG ROM provided as part of the TERN EV/DV software kits for communication with the PC. As a result, you will not be able to debug code directly written for serial port 0.
  • Page 30 Function Argument Baud Rate 1200 2400 4800 9600 19,200 (default) 38,400 57,600 76,800 115,000 230,000 460,800 1 Meg Table 4.1 Baud rate values After initialization by calling s1_init(), SER1 is configured as a full-duplex serial port and is ready to transmit/receive serial data at one of the specified 16 baud rates.
  • Page 31 There is a data structure containing important serial port state information that is passed as argument to the TERN library interface functions. The COM structure should normally be manipulated only by TERN libraries. It is provided to make debugging of the serial communication ports more practical. Since it allows you to monitor the current value of the buffer and associated pointer values, you can watch the transmission process.
  • Page 32 unsigned char dtr; unsigned char en485; unsigned char err; unsigned char node; unsigned char cr; /* scc CR register unsigned char slave; unsigned int in_segm; /* input buffer segment */ unsigned int in_offs; /* input buffer offset */ unsigned int out_segm; /* output buffer segment */ unsigned int out_offs;...
  • Page 33 Miscellaneous Serial Communication Functions One thing to be aware of in both transmission and receiving of data through the serial port is that TERN drivers only use the basic serial-port communication lines for transmitting and receiving data. Hardware flow control in the form of CTS (Clear-To-Send) and RTS (Ready-To-Send) is not implemented.
  • Page 34 Special control registers are used to define how the SCC operates. For a detailed description of registers MR1 and MR2, please see Appendix C of this manual. In most TERN applications, MR1 is set to 0x57, and MR2 is set to 0x07. This configures the SCC for no flow control (RTS, CTS not used/checked), no parity, 8-bit, normal operation.
  • Page 35 The RS485 driver will echo back bytes sent to the SCC. As a result, assuming you are using the RS485 driver installed on another TERN peripheral board, you will need to disable receive while transmitting.
  • Page 36 Access to the EEPROM is quite slow, compared to memory access on the rest of the controller. Part of the EEPROM is reserved for TERN use specifically for this purpose. Addresses 0x00 to 0x1f on the EEPROM is reserved for system use, including configuration information about the controller itself, the jump address for Step Two, and other data that is of a more permanent nature.
  • Page 37 Arguments: int addr Return value: int data This function returns one byte of data from the specified address. 4.6 V104 Sample Programs for DAC & LCD following sample programs supporting the DAC and LCD can be found in the c:\tern\v25\samples\v104 directory: V_ct_da.c...
  • Page 38 V104 Appendix A: V104 Layout Appendix A: V104 Layout All dimensions are in inches. 3.50, 4.00 0.317, 3.825 0.125, 3.850 3.375, 3.883 J5 24 I/O lines 3.325, 3.733 J3 AD/DA header PAL V104P000 PAL V104P1000 V25 Ports 0.358, 2.225 V25 CPU VE232 interface 3.425, 0.633...
  • Page 39 V104 Appendix B: VE232 Pin Layout Appendix B: VE232 Pin Layout All dimensions are in inches.
  • Page 40 V104 Appendix C: UART SCC2691 Appendix C: UART SCC2691 1. Pin Description D0-D7 Data bus, active high, bi-directional, and having 3-State /CEN Chip enable, active-low input /WRN Write strobe, active-low input /RDN Read strobe, active-low input A0-A2 Address input, active-high address input to select the UART registers...
  • Page 41 V104 Appendix C: UART SCC2691 MR2 (Mode Register 2): Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Channel Mode TxRTS CTS Enable Stop Bit Length (add 0.5 to cases 0-7 if channel is 5 bits/character)
  • Page 42 V104 Appendix C: UART SCC2691 ACR (Auxiliary Control Register): Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BRG Set Counter/Timer Mode and Source Power- MPO Pin Function Select Select Down Mode 0 = Baud...
  • Page 43 V104 Appendix D: RTC72421 / 72423 Appendix D: RTC72421 / 72423 Function Table Address Data Register Count Remarks Value 1-second digit register 10-second digit register 1-minute digit register 10-minute digit register 1-hour digit register PM/AM PM/AM, 10-hour digit register 1-day digit register...
  • Page 44 V104 Appendix E: Serial EEPROM Map Appendix E: Serial EEPROM Map Part of the on-board serial EEPROM locations are used by system software. Application programs must not use these locations. 0x00 Node Address, for networking 0x01 Board Type 0x02 0x03 0x04 SER0_receive, used by ser0.c...
  • Page 45 V104 Appendix F: Software Glossary Appendix F: Software Glossary The following is a glossary of library functions for the V104. void ve_init(void) ve.h Initializes the V25 processor. The following is the source code for ve_init() pokeb(0xfff0,0x02,0x80); /* Set PMC0 P07=CLK */ pokeb(0xfff0,0x01,0xd7);...
  • Page 46 V104 Appendix F: Software Glossary void halt(void) ve.h Enables HALT standby mode, which halts the system clock to reduce power consumption. Peripheral CPU devices (serial ports, timers, DMA ..) will not be effected. System clock restored by interrupt. Reference: ve_halt.c void hitwd(void) ve.h...
  • Page 47 V104 Appendix F: Software Glossary void portt_wr(char vref) ve.h Selects reference voltage for the comparator input port. Var: vref – {0 ... 15} defines reference as follows reference = Vth * vref/16. For vref – 0: reference = Vth. Vth : Threshold voltage ≈ 3.57V Reference: portt.c...
  • Page 48 V104 Appendix F: Software Glossary int ee_wr(int addr, unsigned char dat) veee.h Writes to the serial EEPROM. Var: addr – EEPROM data address dat - data Reference: ve_ee.c int ee_rd(int addr) veee.h Reads from the serial EEPROM. Returns 8-bit data Var: addr –...
  • Page 49 V104 Appendix F: Software Glossary void timer1_init(unsigned char mode, int md0, int tm0); Timer 0, 1 initialization. Var: mode – TMC Timer mode. See ch. 9 for the TMC register tm – Count time for the count down timer. md – Count time for the modulo timer.
  • Page 50 V104 Appendix F: Software Glossary Baud 2400 4800 9600 19,200 (default) 38,400 57,600 76,800 115,000 230,000 460,800 1 Meg Reference: s0_echo.c, s1_echo.c, s1_0.c void scc_init( unsigned char m1, unsigned char m2, unsigned char b, scc.h unsigned char* ibuf,int isiz, unsigned char* obuf,int osiz, COM *c) Serial port 0, 1 initialization.
  • Page 51 V104 Appendix F: Software Glossary Reference: s0_echo.c, s1_echo.c, s1_0.c int putser0(unsigned char ch, COM *c); ser0.h int putser1(unsigned char ch, COM *c); ser1.h int putser_scc(unsigned char ch, COM *c); scc.h Output 1 character to serial port. Character will be sent to serial output with interrupt isr.
  • Page 52 V104 Appendix F: Software Glossary Retrieves a fixed-length character string from the input buffer. If the buffer contains less characters than the length requested, str will contain only the remaining characters from the buffer. Appends a ‘\0’ character to the end of str. Returns the retrieved string length.
  • Page 53 Appendix G: Graphic LCD Interface Appendix G: Graphic LCD Interface A Graphic LCD with 240x64 pixels can be interface to V104 LCD header H1. A special PAL V104LCD0 must be installed replacing V104P100. A special cable matching the pin-out of the GLCD must be custom made.
  • Page 54 V104 Appendix H: Interface to MemCard-A Appendix H: Interface to MemCard-A The following diagrams illustrate how to connect the V104 to the MemCard-A via TTL pins, using a cable. V104-MMA cable J5 24 I/O lines PAL V104P1000 PAL V104P000 HC259 U2...
  • Page 55 COPYRIGHT 1995, STE ALL RIGHTS RESERVED. IORDY /RST VBAT /IORD TXD0 /IOWR RXD0 LCD1 TERN/STE /PPI TXD1 /TIMER RXD1 Title /NMI V104 Size Document Number RN10S1 RN10S1 RN10S1 RN10S1 RN10S1 RN10S1 RN10S1 HDRD20 V104-MAN.SCH Date: January 17, 2000 Sheet 1 of...

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