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A-LINE
G
LB3302
0
PS3301
1
Y/C C OUT
2
A1
CNR OFF
H
3
A2
CORR SIGNAL
4
A3
GND (DNR)
5
SEP IN
6
IC3307
V BLANK
L
7
F
C SYNC
8
TCHC4538AFEL
GND (DNR)
9
SEP C OUT
10
A5
GND (DNR)
11
SEP Y OUT
12
A6
GND (DNR)
13
FSC
14
A7
GND (DNR)
15
DNR 5V
16
MAIN IIC DATA
17
MAIN IIC CLOCK
18
C3404
0.1
E
LB3301
VLP0196
C3403
0.1
D
L3309
33u
PS3302
GND (DNR)
1
VV C OUT
2
GND (DNR)
3
4
C
B
R3322
390
D3303
C3310
MA8027H
0.1
A
NOTE:THE MEASUREMENT MODE OF THE DC VOLTAGE IN THE BRACKEST( )ON THIS DIAGRAM IS RECORD MODE
WITH PAL COLOUR SIGNAL.(SP MODE)
THE MEASUREMENT MODE OF THE DC VOLTAGE OUT OF THE BRACKETS ON THIS DIAGRAM IS PLAYBACK MODE
WITH PAL COLOUR SIGNAL.(SP MODE)
1
2
VIDEO MAIN SIGNAL PATH IN REC MODE
V BLK
VR3001
R3326
100KB
5600
R3323
110K
TL3304
D3304
C3324
MA142K
0.015
IC3301
C1AB00001312
5.0
0
4.7
5.0
4.7
0.4
4.7
16
15
14
13
12
11
10
9
(MULTIVIBRATOR)
1
2
3
4
5
6
7
8
0
4.4
5.0
0.4
5.0
0.7
4.4
TL3303
R3324
C3329
22K
470P
H BLK
VR3002
50KB
C3320
C3323
16V10
0.1
K3325
0.01
IC3305
NJM2903M
5.0
1.2
8
7
6
5
+V
-
+
R3310
-
680
+
-V
1
2
3
4
Q3302
4.7
0.4
3.0
2SC3930
4.3
2.5
R3318
(AMP)
(2.9)
22K
R3319
2700
2.4
R3312
1.7
620
R3317
C3322
C3309
100K
R3311
6V47
1000P
560
3
4
VIDEO MAIN SIGNAL PATH IN PLAYBACK MODE
LB3307 VLP0145
LB3306 VLP0145
C3307
33P
C3308
C3302
C3303
C3301
0.01
0.01
680P
0.01
R3302
330
C3304
C3305
0.1
R3301
16V10
0
1.6
3.7
3.5
3.4
2.9
2.9
5.0
2.5
28
27
26
25
24
23
22
21
20
19
C
VSS1
Y
VSS4
VDD4
PLL
DAC
DAC
VCO
1/2
DET
8fsc
4fsc
1/8
(8fsc)
CORING
Y/C SEP.
MIX
MIX
PED.
LPF
+
+
DELAY
& SKEW
ON
OFF
CLIP
CNR
LINE
MEMORY
PEAKING
+
LINE N.C
KILLER
Y/C SEP.
& SKEW
INTERPOLATION
CNR
DYNAMIC COMB
FILTER
CNR
ADC
SYNC
Y/C SEP.
CLAMP
& SKEW
CENTER
BIAS
CNR
VDD1
VSS2
Y+C
TEST
VDD3
1
2
3
4
5
6
7
8
9
10
11
1.3
3.1
5.0
2.5
1.8
2.4
0
0.8
0.4
C3312
C3314
C3315
C3316
C3317
R3305
R3306
0.01
0.01
0.1
0.1
0.47
0
0
L3303
22u
L3302
C3311
C3313
22u
0.1
16V10
R3315
680
Q3301
5.0
2SB1218A
(INV.)
R3313
L3304
1K
27u
2.5
(2.9)
C3327
1.8
8P
(2.2)
Q3303
2SB1218A
C3326
C3328
R3314
(AMP)
12P
12P
3300
NOTE:DO NOT ANY PART NUMBER SHOWN ON THIS SCHEMATIC DIAGRAM FOR
ORDERING.WHEN YOU ORDER A PART,PLEASE REFER TO PARTS LIST.
5
6
5.0
Q3325
3.5
2SD1819A
(AMP)
2.9
R3327
L3307
L3301
1K
22u
22u
R3303
R3304
C3306
L3306
0.1
100
100
39u
L3308
10u
C3334
C3336
47P
56P
0.4
0
2.6
2.8
18
17
16
15
R3334
390
IIC BUS
5.0
3.7
Q3326
V-ENHANCER
3.0
2SD1819A
(AMP)
R3320
1K
LINE
R3331
C3331
MEMORY
1800
8P
5.0
R3338
1200
Q3310
2.7
2SD1819A
SKEW
(AMP)
CORRECT
2.7
2.1
2.0
R3335
R3339
470
1200
SKEW
DET
R3391
VSS3
VDD2
18K
12
13
14
5.0
5.0
0
R3390
1K
C3419
0.01
R3307
C3319
C3321
10K
0.1
0.1
IC3306
TA1225N
5.0
2.5
20
19
LB3308
C3318
VLP0145
16V10
APC
DET
1
2
2.9
L3318
22u
C3427
C3415
C3428
0.1
16V10
4.7
L3317
22u
7
8
9
A-LINE
R3329
2700
TL3301
R3330
R3343
1800
1800
1.8
L3319
L3320
27u
15u
Q3307
1.2
2SB1218A
(BUFFER)
1.3
C3343
C3344
R3328
33P
10P
750
0.6
Q3327
2SB1819A
(INV.)
R3342
620
C3337
C3338
R3325
0.1
6V47
2700
2.6
C3332
Q3305
3P
1.9
2SB1218A
(AMP)
L3305
R3321
47u
1800
C3333
12P
R3336
C3341
22K
0.1
Q3311
2SC3930
(AMP)
C3340
0.01
1.7
R3337
12K
R3341
1K
C3426
0.01
C3420
C3421
C3423
C3424
C3425
0.1
0.1
0.01
0.1
4700P
R3392
C3422
0.01
820
0
2.5
2.0
2.5
2.5
1.4
10.2
2.2
18
17
16
15
14
13
12
11
FO
B.P.F
VOB
VGG
LIM
ADJ
+
+
K
S/H2
AGC
APC
+
CLOCK
PLL
S/H1
LOGIC
4
AGC
BIAS
DET
CCD
906.5BIT
3
4
5
6
7
8
9
10
5.0
2.6
2.4
2.8
5.0
2.4
C3433
0.01
C3430
0.01
C3429
C3431
C3432
1
0.1
16V10
NV-HS825EG/B/EC
DNR PACK SCHEMATIC DIAGRAM
10
11
A6
A5
A7
A1
A2
A3
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