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Related Manuals for Aim APE1553-1-DS
Summary of Contents for Aim APE1553-1-DS
- Page 1 Hardware Manual APE1553-1/2(-DS) Single/Dual Stream MIL-STD-1553 PCI Express Card AIM GmbH Sasbacher Str. 2 79111 Freiburg, Germany Tel: +49-761-45229- 0 Fax: +49-761-45229- 33 sales@aim-online.com www.aim-online.com May 2015 V01.01 Rev. B...
- Page 3 APE1553-1/2(-DS) Hardware Manual Single/Dual Stream MIL-STD-1553 PCI Express Card V01.01 Rev. B May 2015 AIM No: 60-111Dx-16-0101-B...
- Page 4 Notice: The information that is provided in this document is believed to be accurate. No responsibility is assumed by AIM for its use. No license or rights are granted by implication in connection therewith. Specifications are subject to change without notice.
- Page 5 DOCUMENT HISTORY Version Cover Date Created by Description V01.00 Rev-A 08.09.2011 F.Scherer First Released Version V01.00 Rev-B 16.09.2011 F.Scherer Some corrections V01.00 Rev-C 21.09.2011 F.Scherer Some extensions V01.00 Rev-D 10.11.2011 F.Scherer Table for B2B connector > +5V and +3.3V removed •...
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Page 6: Table Of Contents
How This Manual is organized ....................2 Applicable Documents ....................... 2 1.3.1 Industry Documents ......................... 2 1.3.2 Product Specific AIM Documents .................... 2 Installation ......................3 Preparation and Precaution for Installation ................3 Installation Instructions ......................3 Frontpanel-Connectors ......................4 2.3.1... - Page 7 LIST OF FIGURES Figure 2.3-1: DSUB9 Frontpanel-Connector, Pin1 ............4 Figure 2.3.2-1: HD-DSUB26 connector, Pin1 ..............5 Figure 2.3.2.2-1: B2B IRIG Master/Slave Jumper (J0504) ..........7 Figure 3.2.2.3-1 Discrete I/O-Pin ..................9 Figure 3.2.2.3-2 Discrete Output protection ..............10 Figure 2.4-1: B2B Connector for 16-pin ribbon cable ............ 12 Figure 2.4-2: Example for a Ribbon Cable connection ..........
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Page 9: Introduction
For programming information please refer to the documents listed in the ‘Applicable Documents’ section. The APE1553 modules are members of AIM's new family of advanced PCI Express cards compliant to PCI Express V1.1. The PCI Express Interface is 1-lane wide and working with 2.5 Gbit/s in transmit and receive direction. -
Page 10: How This Manual Is Organized
AIM - APE1553 Getting Started Manual Assists the first time user with software installation, hardware setup and starting a sample project. AIM - Reference Manual APE1553 Application Interface Library Provides a detailed description of the programming interface. AIM – APE1553 Programmer's Guide... -
Page 11: Installation
INSTALLATION 2.1 Preparation and Precaution for Installation This module features full PCI Express Plug and Play capability; therefore, there are no jumpers or switches on the board that require modification by the user in order to interface to the PCI bus. It is recommended to use a wrist strap for any installations. -
Page 12: Frontpanel-Connectors
2.3 Frontpanel-Connectors The external interface of the APE1553 provides of up to two dual redundant MIL-STD- 1553 channels, Trigger In/Out signals, as well as the IRIG In/Out signals for time tag synchronization. The MILbus interface is provided on a female DSUB9 connector and the Trigger In/Out, IRIG and GPIO signals are provided on a HD DSUB26 connector. -
Page 13: Trigger, Irig And General Purpose Discrete-I/O (Gpio) Interface Connector
2.3.2 Trigger, IRIG and General Purpose Discrete-I/O (GPIO) Interface Connector The Trigger, GPIO and IRIG signals are provided on a High-Density DSUB26 female connector. The RS232 signals are for maintenance purposes only. Pin No. Signal RS232 RXD Trigger Output BC, Channel 1 Trigger Input BC, Channel 1 Trigger Output BC, Channel 2 (APE1553-2 only) -
Page 14: Trigger Connection
Multiple AIM-Modules with no common synchronization requirement - No connection required Case 3: Single or multiple AIM-Module(s) with external IRIG-B source - Connect external IRIG-B source to IRIG-IN and GND of all modules Case 4: Multiple AIM-Modules with no external IRIG-B source internally synchronized. -
Page 15: Figure 2.3.2.2-1: B2B Irig Master/Slave Jumper (J0504)
The figure below shows the IRIG Master/Slave jumper (J0504) on the APE1553: Pos1 Pos2 Pos3 Figure 2.3.2.2-1: B2B IRIG Master/Slave Jumper (J0504) If the board should receive the IRIG signal, it has to be in IRIG Slave-Mode, if the board should transmit the IRIG signal, it has to be switched to IRIG Master-Mode. -
Page 16: Gpio Connection
2.3.2.3 GPIO connection The APE1553 provides eight General Purpose Discrete I/O's (GPIO’s). Five General Purpose I/O's (GPIO1 - GPIO5) are provided at the HD-DSUB26 frontpanel connector with Avionic Level inputs and outputs. All eight GPIO's are provided on the B2B-Connector. The GPIO’s can be used as simple discrete inputs or outputs, for example to generate strobes (i.e. -
Page 17: Figure 3.2.2.3-1 Discrete I/O-Pin
Discrete IO-Pin Front/Rear Connector Onboard APE1553-x Input-Pin Current Current FPGA limiting limiting Resistor Resistor 1 kOhm 10 kOhm Output-Pin FPGA Pulldown Resistor Ground Ground Discrete input circuitry Discrete output circuitry Figure 3.2.2.3-1 Discrete I/O-Pin APE1553-1/2(-DS) Hardware Manual... -
Page 18: Figure 3.2.2.3-2 Discrete Output Protection
Offboard User User serial Customized Discrete IO-Pin Discrete Front/Rear Connector APE1553-x Output-Pin FPGA Figure 3.2.2.3-2 Discrete Output protection APE1553-1/2(-DS) Hardware Manual... -
Page 19: Rs232 Connection
2.3.2.4 RS232 connection For debugging purposes and board maintenance a RS232 interface is provided. To establish a RS232 communication link between the APE1553 and a PC – COM-Port the RS232-TXD/-RXD signals from the 26-pin high density DSUB-Connector have to be connected with the RS232-TXD/-RXD signals from the PC via a NULL-Modem connection. -
Page 20: Board To Board Connector (B2B Connector)
2.4 Board to Board Connector (B2B connector) The Board to Board connector provides the eight General Purpose Discrete I/O signals (GPIO’s) and an additional “one pin” combined IRIG-B Master-Output/Slave Input on a 16-pin ribbon cable connector (mounted on the upper right corner, see figure the figure below). -
Page 21: Figure 2.4-2: Example For A Ribbon Cable Connection
Figure 2.4-2: Example for a Ribbon Cable connection If there is a requirement to provide the B2B connector signals externally (outside the PC), an optional AIM Breakout-Panel, which occupies one PC-Slot, can be used to break out the signals. The Breakout Panel is available on request, please contact the factory. -
Page 22: Front Panel Led's
2.5 Front Panel LED’s Four sub miniature LED's indicates the various conditions of the module at the front panel. The LED's are located in a quadruple LED-Array on the physical bus interface daughterboard. LED Name Colour Description FAIL1 LED illuminates if an Error during the BIU 1 self-test occurs. COUPLED / Green - LED illuminates permanently if the MILbus channel 1 is connected. -
Page 23: Structure Of The Ape1553-1/-2
STRUCTURE OF THE APE1553-1/-2 The structure of the APE1553 card is shown in the block diagram. The APE1553-1/-2 comprises the following main sections: PCI Express Interface and BIU-IO FPGA Global RAM BIU Section Physical I/O Interface with up to two Dual redundant MIL-STD-1553 busses ... -
Page 24: Pci Express Interface And Biu-I/O Fpga
3.1 PCI Express Interface and BIU-I/O FPGA The new common FPGA architecture of AIM’s new family of PCI Express based modules includes both the complete PCI Express bus logic and the BIU processor logic. The FPGA implements the following features: PCI Express 1.1 compliant bus interface... -
Page 25: Irig-B Encoder/Decoder And Timecode Processor (Tcp)
3.1.6 IRIG-B Encoder/Decoder and Timecode Processor (TCP) The IRIG-B time code will be received and decoded from the Timecode-Processor. The decoded millisecond time code received from TCP is expanded by a self-generated microsecond value and organized to a 46Bit time tag value. The format is shown below: Time Element Number of bits... -
Page 26: Global Ram
3.2 Global RAM The Global RAM is shared between both BIU processors (BIP) and the Host PCIe-Bus. The arbitration is handled by the common FPGA. It has access to the common Global RAM via a 32 bit wide data port. 3.3 BIU Section Up to two Bus Interface Units (BIUs) are implemented on the module using low power, high performance 32bit RISC processors. -
Page 27: Figure 3.4-1: Milbus Coupling Modes
Figure 3.4-1: MILbus Coupling Modes MIL-BUS Isolated (default) No connection to the MILbus MIL-BUS Transformer Coupled MIL-BUS Direct Coupled MIL-BUS Transformer Coupled with Network Emulation In network emulation mode, the MILbus emulation circuitry emulates a transformer- coupled network without the use of MILbus couplers (using a resistor network). Thus, an external dual-redundant MIL-STD-1553 Terminal can be directly connected to the module. -
Page 28: Voltage Supplies
The following figure shows the typical MILbus Amplitude [in %] versus the 8Bit DAC value [in Dec]. 8Bit DAC value Figure 3.4-2: MILbus Amplitude vs. DAC value 3.5 Voltage Supplies All required on board supply-voltages are either generated on board using switching power supplies or have to be provided by the System (PC) power supply. -
Page 29: Milscope Functionality
MILSCOPE FUNCTIONALITY This section describes the functionality of the MILScope part on an APE1553-1/2-DS module and are only available on the –DS (digital scope) versions. On an APE1553-2-DS module, the MILScope functionality is only available for MILbus Channel 1. tructure of the APE1553-1/2-DS The function of the MILScope is divided into two main parts, the coupling and data conversion on the PBI (Physical Bus Interface), and the data analysis implemented in the FPGA on the Mainboard. -
Page 30: Milscope Pbi Section
4.1.1 MILScope PBI section The MILScope part on the PBI has two main tasks, the first one is the coupling of the Analogue to Digital Converter inputs to different sources, and the second is the conversion from the analogue input signals to digital values. A relay circuitry is used to couple the input of the A/D-Converter to different sources and voltage ranges. -
Page 31: Implemented Milscope Functions
A Burst data memory is implemented in the FPGA, to store data in fast acquisition modes (single shot, 50MSamples 2 busses or 100MSamples 1 bus), or used as a buffer in slower acquisition modes (continues mode). Notes: 50MSample-Mode means 49,5Msamples/s and 100Msample-Mode means 99MSamples/s. In 100MSample mode and in 50MSamples 2channel mode, the data storage is limited to 6kByte. -
Page 32: Input Filter And Noise
4.2.2 Input Filter and Noise Low pass filters are implemented for high frequency suppression and impedance matching between the amplifier stage and the A/DC input. On sampling rates higher than 20ns (40ns…) the average value of the last two samples is saved, which results in a better SNR. -
Page 33: Technical Data
TECHNICAL DATA PCI Express bus: Compatible with PCI-Express Standard (Release 1.1) 3.3V PCI Express card Single Lane PCI Express bus operation 2.5 Gbit/s Memory: 128 Mbyte DDR2-RAM 1x SPI-Flash for FPGA 2x SPI-Flash for BIUs BIU-Section: Low power, high performance 32bit RISC Processor(s) Encoder: For each BIU, one Manchester Encoder with Parity generator and error injection. - Page 34 MIL-STD-1553 Bus Front End: The physical I/O Interface comprises a one/two dual redundant MIL-STD- 1553 stream(s). It consists of the MIL-STD-1553 trapezoidal transceiver and a respective transformer. The output voltage of the transceiver is programmable (separate for primary and secondary channel): app. 0V … >21VPP transformer coupled into 70 OHM.
- Page 35 Connectors: DSUB9 Frontpanel-Connector MIL-Bus: MIL-STD-1553 isolated, transformer or direct coupled stub connections. Emulates a 70 Ohm transformer coupled network stub if programmed accordingly. HD-DSUB26 Frontpanel-Connector Trigger In: TTL-Input, 1.5 k Pulldown and 220pF EMV capacitor. Rising Edge sensitive, Pulse width > 75ns Trigger Out: TTL-Output with 82 Ohm series resistor, 220pF EMV capacitor, High Pulse width strobe, 500ns duration.
- Page 36 IRIG-I/O: Additional “one pin” IRIG input/output channel. IRIG-Input (slave-mode) IRIG-Output (master-mode). Master/Slave-Mode can be set via jumper USB connectors and Through-Hole Micro Header For board maintenance and JTAG support. MILScope Function: AD-Converter: Sampling Rate: 50MSamples (100MSamples interleave) Resolution: 10Bit Horizontal Functions: Sampling Rate: 1 channel mode 10ns...5,1µs 2 channel mode 20ns...5,1µs...
- Page 37 Working Idle + 3.3V 2.9 W 2.8 W 2.8 W 2.8 W + 12.0V 6.6 W 3.5 W 0.6 W APE1553-2-DS APE1553-1-DS Voltage Working idle Working Idle + 3.3V 4.4 W 4.3 W 4.4 W 4.3 W + 12.0V 8.8 W 2.6 W...
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Page 39: Notes
NOTES 6.1 Acronyms Analog to Digital Converter Advanced RISC Machine Application Support Processor Board to Board Bus Controller Bus Monitor Bus Interface Processor Bus Interface Unit Board Software Package Digital to Analog Converter. DDRRAM Double Data Rate Random Access Memory DRAM Dynamic Random Access Memory EEPROM...
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