MEN F405 User Manual

Railway i/o card – data acquisition & control
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20F405-00 E2
2019-04-26
F405
Railway I/O Card – Data Acquisition & Control
3U CompactPCI
User Manual

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Summary of Contents for MEN F405

  • Page 1 20F405-00 E2 2019-04-26  F405 Railway I/O Card – Data Acquisition & Control 3U CompactPCI User Manual...
  • Page 2: Table Of Contents

    Using the F405 under Linux ........
  • Page 3 Product label............17 Figure 5. MDIS wizard configuration for F23P CPU with one F405 (example) ..20 Figure 6.
  • Page 4: About This Document

    This document is intended only for system developers and integrators. It describes the design, functions and connection of the product. The manual does not include detailed information on individual components (data sheets etc.). F405 product page with up-to-date information and downloads: www.men.de/products/f405/ History...
  • Page 5 About this Document Conventions Indicates important information or warnings concerning situations which could result in personal injury, or damage or destruction of the component. Indicates important information concerning electrostatic discharge which could result in damage or destruction of the component. Indicates important information or warnings concerning proper functionality of the product described in this document.
  • Page 6: Product Safety

    Only store the product in its original ESD-protected packaging. Retain  the original packaging in case you need to return the product to MEN for repair. Qualified Personnel The product/system described in this documentation may be operated only by personnel qualified for the specific task in accordance with the relevant documentation, in particular its warning notices and safety instructions.
  • Page 7: Product Compliance

    Technical Data and thus enable you to achieve certification of the product according to the standards applicable in your field of application. If the product delivered was certified by MEN and is modified by the customer, e.g., by installing an additional hardware component, the certification achieved by MEN becomes invalid and has to be repeated for the new product configuration.
  • Page 8: Disclaimer

    MEN was negligent regarding the design or manufacture of the part. In no case is MEN liable for the correct function of the technical installation where MEN products are a part of.
  • Page 9: Contacts

    860 Penllyn Blue Bell Pike Room 1215, #993 West Nanjing Road Blue Bell, PA 19422 Shanghai 200041 Phone 215-542-9575 Phone +86-21-5058-0963 sales@menmicro.com info@men-china.cn www.menmicro.com www.men-china.cn Copyright © 2019 MEN Mikro Elektronik GmbH. All rights reserved. 20F405-00 E2 2019-04-26 Page 9 ...
  • Page 10: Product Overview

    Designed for Harsh Environments The F405 is designed for operation in a -40°C to +85°C temperature range according to EN 50155 class TX. The coated board withstands shock and vibration for reliable operation and a longer product life-time.
  • Page 11: External Interfaces

    Product Overview External Interfaces Figure 1. Front interfaces ® CompactPCI F405 20F405-00 E2 2019-04-26 Page 11 ...
  • Page 12: Board Layout

    Product Overview Board Layout Figure 2. Board layout – top view Heat sink Code comb 48-pin front connector CompactPCI connector J1 20F405-00 E2 2019-04-26 Page 12 ...
  • Page 13: Block Diagram

    Product Overview Block Diagram Figure 3. Block diagram 32 LEDs Isolated groups Analog Out Digital In  0 ‐ 3 Digital In  FPGA 4 ‐ 7 Digital Out Pulse Counter  PWM Out F Front Rear 20F405-00 E2 2019-04-26 Page 13 ...
  • Page 14: Technical Data

    Product Overview Technical Data Digital Inputs Eight channels  Two isolated groups Input voltage  -110 V to +110 V Logical High: -110 V to -9 V and +9 V to +110 V Logical Low: -5 V to +5 V Input current ...
  • Page 15 Product Overview Output current  10 mA max. per channel PWM cycle length  Software configurable 2 μs to 65535 μs PWM pulse length  Software configurable 0 μs to 65535 μs Pulse Counter Inputs Two channels  One isolated group Frequency measurement: 0.1 Hz to 30 kHz Optocoupler input Supported sensors...
  • Page 16 Product Overview Weight  358 g (with heat sink) (model 02F405-00) See the MEN website for a detailed 3D drawing (PDF and STEP file): www.men.de/products/f405/#doc Environmental Specifications Temperature range (operation)  -40°C to +85°C (qualified components), compliant with EN 50155, class TX (model 02F405-00, 02F405-01) Temperature range (storage): -40°C to +85°C...
  • Page 17: Product Identification

    Product Identification MEN documentation may describe several different models and design revisions of the F405. You can find the article number and design revision affixed to the F405. Article number: Indicates the product family and model. This is also MEN’s main ...
  • Page 18: Getting Started

    2.1.1 Coding the Front Connector The front connector of the F405 can be coded to prevent plugging a wrong connector. If applicable, you can code the front connector on the code comb with code pins according to the coding of the mating connector.
  • Page 19: Using The F405 Under Linux

    » Add all 16Zxxx IP cores to the MEZZ_CHAM model of the F405 board. For this, use the next free FPGA internal slot. » Specify the device name and chameleon instance number.
  • Page 20: Mdis Example Programs And Tools

    Note: You can also create an MDIS project automatically using the scan_system function. Figure 5. MDIS wizard configuration for F23P CPU with one F405 (example) 2.4.2 MDIS Example Programs and Tools After installing the driver on the target system, you can find the following resources in...
  • Page 21: Fpga Utility Usage

    Note: For detailed usage information, call the programs without any arguments.  The F405 operates with a system clock frequency of 1MHz. For the z61_ctrl tool, you have to specify this frequency in Hz as parameter -f=1000000. # z61_ctrl pwm_1 -f=1000000...
  • Page 22: Functional Description

    3.2.1 Watchdog The FPGA of the F405 provides a watchdog function which puts the outputs into a safe state if the host software has crashed or the host interface is not working correctly. If enabled, the watchdog must be triggered by application software. The watchdog timeout can be set to 93.75 ms, 187.5 ms, 375 ms, 750 ms, 1500 ms or 3000 ms.
  • Page 23: Status Leds

    Functional Description Status LEDs Table 3. Status LEDs at front panel Appearance Label Color Function Green Indicates functioning of the board On: Correct operation  Off: Board is not in correct operation state  Indicates state of the outputs On: Outputs are in safe state ...
  • Page 24: Front Connector

    Functional Description Front Connector Table 4. Pin assignment – front connector ANA_V_OUT_0 ANA_GND_0 ANA_I_OUT_0 ANA_V_OUT_1 ANA_GND_1 ANA_I_OUT_1 DIG_IN_2 DIG_IN_1 DIG_IN_0 DIG_IN_4 DIG_IN_3 DIG_IN_GND_A DIG_IN_GND_B DIG_IN_6 DIG_IN_5 DIG_IN_7 DIG_OUT_VS- DIG_OUT_2 DIG_OUT_1 DIG_OUT_0 FWD_B DIG_OUT_3 FWD_A DIG_OUT_5 DIG_OUT_4 DIG_OUT_VS+ DIG_OUT_7 DIG_OUT_6 DIG_OUT_VS+ DIG_OUT_9 DIG_OUT_8 FWD_CD...
  • Page 25: Isolation Voltages

    3.6.1 Operating Principle The voltage applied to each digital input of the F405 may be either positive or negative referenced to the corresponding DIG_IN_GND. The software can advice the device to send a signal to the application when the input changes.
  • Page 26: Current Sink

    If the logical state of the input is low, the current is permanently on. 3.6.3 Software Support Chapter 2.4 Using the F405 under Linux on page 19 for the applicable driver for software configuration. Digital Outputs...
  • Page 27: Operating Principle

    3.7.1 Operating Principle The digital outputs of the F405 are high-side switches, i.e. they connect or disconnect a load to a supply voltage. The outputs are supplied by an external voltage (DIG_OUT_VS+). The FPGA activates the digital output switch, realized by an opto relay, providing the voltage supplied via DIG_OUT_VS+ on the digital output pin.
  • Page 28: Temperature Derating

    Functional Description 3.7.2 Temperature Derating The maximum output current of the digital outputs of the F405 derates with increasing board ambient temperature. If the maximum output current is exceeded, the output will be disabled. Chapter 3.7.3 Protection Functions on page Figure 7.
  • Page 29: Analog Outputs

    3.8.1 Operating Principle The analog outputs of the F405 provide the output value on one pin as voltage and on one pin as current. The desired output value defined by software is converted in the FPGA and via the digital-to-analog converter supplied on the outputs.
  • Page 30: Pwm Outputs

    3.9.1 Operating Principle The pulse width modulation (PWM) outputs of the F405 are push/pull outputs, set to logical low state or high state by the FPGA. After power up or watchdog timeout, the outputs are in logical low state which is the default state.
  • Page 31: Software Support

    Software configurable Detection time: 10 ms to 2550 ms 3.10.1 Operating Principle The pulse counter inputs of the F405 are connected to one frequency counter in the FPGA. The inputs can be used to connect a speed sensor. 20F405-00 E2 2019-04-26 Page 31 ...
  • Page 32: Input Signals

    32) or to the negative pin PC_IN (see Figure 11, Pulse counter input – sensor connected to PC_IN on page 33) of the respective pulse counter input of the F405. Figure 10. Pulse counter input – sensor connected to PC_IN_V+ Power ...
  • Page 33: Frequency Measurement

    3.10.4 Rolling Detection and Standstill Detection Rolling or standstill detection is done in the FPGA of the F405. The respective time period for the detection can be configured in the FPGA. Rolling status is set to true, if the time between two successive edges (rising or falling) on any input signal is smaller than the configured rolling time period.
  • Page 34: Distance Measurement

    Functional Description 3.10.6 Distance Measurement For distance measurement in the F405, the FPGA counts sensor pulses. Forward measurement is always possible, backward measurement is only possible when a sensor with phase shifted signal is used. If only one signal is available, and the other signal remains at a static level, then the distance counters can still be used.
  • Page 35: Hardware/Software Interface

    0x5A14 Subsystem Vendor ID:  0x00D6 FPGA IP Core Implementation The functions of the F405 are controlled using IP cores in an FPGA. See the following table for a list of the IP cores. Table 7. Chameleon table Name Device...

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