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Novatek NT6861 Manual

8-bit microcontroller for monitor

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Features
n 40 pin DIP & 42 pin SDIP package
n Operating Voltage Range: 4.5V to 5.5V
n CMOS
technology
n Crystal oscillator or ceramic resonator* available
n 6502 8-bit CMOS CPU core
n 8MHz operation of frequency
n 4/8/12/16/24K bytes ROM are available
n 256 bytes of RAM (which stores EDID for DDC1/2B)
n One 8-bit pre-loadable base timer
n 14 channels of 8 bit PWM outputs:
6 channel with 5V open drain and 8 channel with 12V
open drain
n 2 channel A/D converters with 6-bit resolution
General Description
NT6861 is a monitor component µC for auto-sync and
digital controlled applications. It contains a 6502
8-bit CPU core, 256 bytes of RAM used as working RAM
and stack area, 24K bytes of ROM maximum for
programming, 14-channel 8-bit PWM D/A converters, 2-
channel A/D converters for key detection saving I/O pins,
one 8 bit pre-loadable base timer, internal Hsync and
Vsync signals processor providing mode detection,
watch-dog timer preventing system from abnormal
2
operation, and an I
C bus interface.
for
low
power
consumption
8-Bit Microcontroller for Monitor
n 24 bi-directional I/O port pins and 1 I/P pin
n Hsync/Vsync signal processor
n Hardware sync signals polarity & freq. evaluator
n Built-In I
2
C bus interface
n Supporting VESA DDC1/2B function
n Six-interrupt sources
- INTV (Vsync INT)
- INTE
(External INT with rising edge trigger)
- INTMR (Timer INT )
- INTA
(Slave Address Matched INT)
- INTD (Shift Register INT)
- INTS
(SCL GO-LOW INT)
n Hardware watch-dog timer function
Users can store EDID data in the 128 bytes of RAM for
DDC1/2B, so that users can save the cost of dedicated
EEPROM for EDID. Half frequency output function can
save external one-shot circuit. All of these designs create
savings in component costs.
* The frequency deviation of ceramic resonator has
+/- 6% maximum.
1
NT6861
V2.0

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Summary of Contents for Novatek NT6861

  • Page 1 2 channel A/D converters with 6-bit resolution n Hardware watch-dog timer function General Description NT6861 is a monitor component µC for auto-sync and Users can store EDID data in the 128 bytes of RAM for digital controlled applications. It contains a 6502...
  • Page 2: Pin Configuration

    NT6861 Pin Configuration [OE] DAC2 VSYNCI/INTV VSYNCI/INTV/ [A14] [OE] DAC2 DAC1 HSYNCI DAC1 HSYNCI DAC0 DAC3 [PGM] DAC0 DAC3 [PGM] [VPP] RESET DAC4 [MODE0] DAC4 [MODE0] [VPP] RESET DAC5 [MODE1] DAC5 [MODE1] DAC6 [MODE2] DAC6 [MODE2] DAC7 OSCO OSCO P07/HSYNCO [A7]...
  • Page 3 NT6861 Pin Descriptions Pin No. Designation Reset Init. Description 40 Pin 42 Pin DAC2 Open drain 12V, D/A converter output 2 DAC1 Open drain 12V, D/A converter output 1 DAC0 Open drain 12V, D/A converter output 0 Schmitt trigger input pin, low active reset*...
  • Page 4 NT6861 Pin Descriptions (continued) Pin NO. Designation Reset Init. Description 40 Pin 42 Pin Open drain 5V Bi-direction I/O pin P30, shared with SDA pin of P30/SDA C bus schmitt trigger buffer Open drain 5V Bi-direction I/O pin P31, shared with SCL pin of...
  • Page 5: Functional Descriptions

    NT6861 Functional Descriptions 1. 6502 CPU The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true indexing capability, programmable stack pointer with variable length stack, a wide selection of addressable memory, and interrupt input options.
  • Page 6 NT6861 2. Instruction set list Instruction Code Meaning Operation A + M + C → A, C Add with carry M → A Logical AND • C ← M7 M0 ← 0 Shift left one bit • • • Branch if carry clears...
  • Page 7 NT6861 Instruction set list (continued) Instruction Code Meaning Operation (PC+1) → PCL, (PC+2) → PCH Jump to new location PC + 2 ↓, (P+1) → PCL, (PC+2) → PCH Jump to subroutine M → A Load accumulator with memory M → X Load Index register X with memory M →...
  • Page 8 NT6861 3. RAM: 256 X 8 bits 256 X 8-bit SRAM is used for data memory and stack. The RAM addressing range is from $0080 to $017F. From $0100 to $017F is used as the EDID data buffer when activating DDC1/2B mode transmission. The contents of RAM are undetermined at power-up and are not affected by system reset.
  • Page 9 NT6861 4. System Registers Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 $0000 $0001 $0002 PT2DIR P27OE P26OE P25OE P24OE P23OE P22OE P21OE P20OE $0003 $0004 $0005 MD CON MD1/ MD1/ INSEN HSEL $0006 HV CON HCNTOV...
  • Page 10 NT6861 System Registers (continued) Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 $0010 IRQX IRQINTS IRQINTD IRQINTA IRQINTR IRQINTE IRQINTV $0011 CLR FLG CLRHOV CLRVOV CLRINTS CLRINTD CLRINTA CLRINTR CLRINTE CLRINTV $0012 CLR WDT $0013 II ADR...
  • Page 11 NT6861 5. Timing Generator This block generates the system timing and control signal to be supplied to the CPU and on-chip peripherals. A crystal quartz, ceramic resonator, or an external clock signal provided to the OSCI pin generates 8MHz system clock, (4 MHz for CPU), Although internal circuits have a feedback resistor and compacitor included, components may be externally added to ensure proper operation.
  • Page 12 NT6861 A/D Channel Control Register Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 $000C ENDAC ENAD1 ENAD0 ENDK13 ENDK12 ENDK11 ENDK10 ENDK9 ENDK8 $000D AD0 REG AD05 AD04 AD03 AD02 AD01 AD00 CEND CSTA $000E AD1 REG...
  • Page 13 7. PWM DACs (Pulse Width Modulation D/A Converters) There are 14 PWM D/A converters with 8-bit resolution in NT6861. Eight of these D/A (DAC0 - DAC7) converters are open- drain output structures with 12V applied (maximum), and the other six D/A converters (DAC8 - DAC13) are open-drain output structures with 5V applied (maximum).
  • Page 14 NT6861 Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 $000C ENDAC ENAD1 ENAD0 ENDK13 ENDK12 ENDK11 ENDK10 ENDK9 ENDK8 $0018 DACH0 DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 $0019 DACH1 DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2...
  • Page 15 DAC8 - DAC13 is disabled 8. RESET 8. Watch-dog timer is cleared and enabled NT6861 can be reset by the external reset pin or by the internal watch-dog timer. This resets or starts the This RESET pin must be pulled high by external pulled-up microcontroller from a power-down condition.
  • Page 16 - INTA INT (Address Matched INT): External device interrupt sources is active by checking the IRQX. Upon calling NT6861 in DDC2 mode communication entering the interrupt service routine, the IRQX that caused - INTD INT (Shift Register INT): Shift register is the interrupt service must be cleared in the interrupt empty or receiving a new byte data in DDC1 &...
  • Page 17 11. I/O PORTs signal can be read. This port outputs high after reset . NT6861 has 25 pins dedicated to input and output. These P00 - P05 are shared with DAC8 - DAC13 respectively. If pins are grouped into 4 ports .
  • Page 18 NT6861 11.2. Port1: P10 - P16 Port10-Port15 are 6-bit bi-directional CMOS I/O ports with P12, P13 are shared with half signals input and output pins PMOS as the internal pull-up (Figure 6). Port16 is an input by accessing SYNCON control register. If user clears the pin only.
  • Page 19 NT6861 11.3. Port2: P20 - P27 Port2, an 8-bit bi-directional I/O port (Figure 10), which may be programmed as an input or output pin by the software control. When setting the PT2DIR control bit to '0', its corresponding pin will act as output pin. Clearing PT2DIR bit to '1', acts as an input pin.
  • Page 20 NT6861 12. H/V sync signals processor The functions of the sync processor include polarity VCNTOV bit (in HVCON register) to HIGH (see Figure 14). detection, Hsync & Vsync signals counting, programmable Once the VCNTOV sets to HIGH, it keeps in HIGH state...
  • Page 21 NT6861 Latch VCNT register Latch VCNT register Reset V sync. counter Reset V sync. counter Start pulse counting Start pulse counting VSYNCI Sampling Clock 8µ s Figure 14. Vsync counter Operation Latch HCNT register Latch HCNT register Reset H sync. counter Reset H sync.
  • Page 22 NT6861 VCNTL VCNTH Control Enable Logic V sync. Latch Enable 8 µs VSYNC Schmitt Digital V sync. Reset Trigger Filter counter INPUT HSEL 8.192 ms Enable H sync. Reset counter Enable H sync. H & V Latch Sync. HSYNC Digital...
  • Page 23 NT6861 12.2. Sync Processor Control Register: Composite sync: User has to determine whether the incoming signal is separate sync or composite sync and Sync output: In pin assignment, VSYNCO & HSYNCO represent Vsync & Hsync output which are shared with set S/ C &...
  • Page 24 NT6861 ● ● ● (1) HSYNCI Composite H sync. waveform (H EOR V) ● ● ● (2) HSYNCI Composite H sync. waveform (H OR V) No matter Hsync pulse existing or not, the output signal of Hsync will be inserted.
  • Page 25 NT6861 Sync. Mode Processing Set S/C = '0' System Default: Freq. Clear VCNTOV & HCNTOV Calculating S/C = '1' & HSEL = '1' Open INTV & clear INTV flag Open INTV & clear INTV flag Set S/C = '1' & HSEL = '0' Clear VCNTOV &...
  • Page 26 NT6861 61Hz Pulse width 64 µ s (a) Free run output Vsync. signal (1) 62.5KHz (2) 41.7KHz Pulse width 1µ s (b) Option 2 of free run output Hsync. signal Figure 20. Free Running Sync. Waveform HALFHI HALFHO: Half freq. output signal (50% duty)
  • Page 27 - '1' for positive polarity and '0' for signal, clear this bit. Under the COMPOSITE mode, negative polarity. NT6861 will extract the V Sync form H Sync HPOLO & VPOLO: To control the output polarity of H & V signal.
  • Page 28 NT6861 positive polarity and '0' for negative polarity HALFPOL: User must clear ENHALF first and control the polarity at the HALFHO output pin - '1' for...
  • Page 29 NT6861 13. BASE TIMER (BT) The Base Timer is an 8-bit counter whose clock source must be chosen with 1µs or 1ms by setting or clearing the TBS bit ('0' for 1µs and '1' for 1ms). The BT can be enabled/disabled by the ENBT bit in the BTCON register. When user clearing this control bit to '0', the BT will start counting, otherwise setting this bit to '1' will stop the counting.
  • Page 30 I C bus is the most important structure. Two modes of operation have been implemented in NT6861: UNI- DIRECTIONAL mode (DDC1 mode) and BI-DIRECTIONAL mode (DDC2B mode). If the MD1/2 bit is set to '1', the device will operate in the DDC1 mode, and if the MD 1/2 bit is cleared to '0', the device will operate in the DDC2B mode.
  • Page 31 NT6861 Control bit description: Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 $0005 MD CON S/ C MD1/ HSEL INSEN S/ C MD1/ $000F IEINTS IEINTD IEINTA IEINTR IEINTE IEINTV $0010 IRQX IRQINTS IRQINTD IRQINTA IRQINTR IRQINTE...
  • Page 32 - SLAVE mode (NT6861 addressed by a master interrupt and switch to DDC2B mode automatically. When which drive SCL signal) user sets MD1/2 to '1' at this time, the NT6861 will still - Fully compatible with I C bus standard proceed with a DDC1 communication.
  • Page 33 The INTD on the READ mode: External device read data Data Transmission direction: At INTA interrupt servicing from NT6861. At INTD interrupt, the SCL will be hold LOW routine, user must check the LSB of address data in IIDAT by NT6861. User can check RXACK bit in the IISTS register.
  • Page 34 SDA while SCL is in HIGH state. When there is mode communication at any time. This function is a STOP condition, NT6861 will set the 'STOP' bit to '1' and supporting the 'error' recovery protocol in the VESA DDC user can poll this status bit to control DDC2B transmission standard Ver 2.0.
  • Page 35 NT6861 NT6861 Address DATA DATA Data transferred from external device From external device to NT6861 A = acknowledge S = START P = STOP From NT6861 to external device (a) WRITE_Mode Data Format wait wait wait wait STOP START (external device)
  • Page 36 NT6861 NT6861 Address DATA DATA Data transferred from external device From external device to NT6861 A = acknowledge S = START A = no acknowledge P = STOP From NT6861 to external device (a) Read_Mode Data Format wait wait wait...
  • Page 37 NT6861 Interrupt Service Routine Polling Need Need Need Need Need Main Program Polling Polling Polling Polling Polling INTS ? INTD ? INTA ? INTV ? INTR ? Open INTV & INTS INTA ? INTV ? INTS ? INTD ? INTR ?
  • Page 38 NT6861 Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum DC Supply Voltage V ....-0.3V to 7V Ratings" may cause permanent damage to this device.
  • Page 39: Ac Electrical Characteristics

    NT6861 AC Electrical Characteristics = 5V, T = 25°C, oscillator freq. = 8MHz, unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit Condition Fsys System Clock µs A/D Conversion time C N V T Voffset A/D Converter Offset Error Vin = 2V for A/D converter...
  • Page 40 NT6861 DDC1 Mode Symbol Parameter Min. Typ. Max. Unit Condition Vsync high time Fvsync Vsync Input Frequency = 1/Fvsync VSYNC Data valid Time for transition to DDC2B MODE mode MODE Bit 0 Null Bit Bit 7 Bit 6 VSYNC Composite ●...
  • Page 41 NT6861 DDC2B Mode Symbol Parameter Min. Typ. Max. Unit fSCL SCL Clock Frequency µs Bus Free Between a STOP and START Condition µs Hold Time for START Condition ; STA µs LOW Period of the SCL Clock µs HIGH Period of the SCL Clock HIGH µs...
  • Page 42 NT6861 Ordering Information Part No. Package NT6861 40L DIP NT6861U 42L S-DIP...
  • Page 43 NT6861 Package Information DIP 40L Outline Dimensions unit: inches/mm Base Plane Seating Plane α Symbol Dimensions in inches Dimensions in mm 0.210 Max. 5.33 Max. 0.010 Min. 0.25 Min. 0.155±0.010 3.94±0.25 0.018 +0.004 0.46 +0.10 -0.002 -0.05 0.050 +0.004 1.27 +0.10 -0.002...
  • Page 44 NT6861 Package Information S-DIP 42L Outline Dimensions unit: inches/mm pin 1 index Base Plane Seating Plane Symbol Dimensions in inches Dimensions in mm 0.200 Max. 5.08 Max. 0.020 Min. 0.51 Min. 0.157 Max. 4.0 Max. 0.051 Max. 1.3 Max. 0.031 Min.