Silicon Laboratories Si5386 Reference Manual

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Si5386 Rev. E Reference Manual

Overview

This Reference Manual is intended to provide system, PCB design, signal integrity, and

software engineers the necessary technical information to successfully use the Si5386

device in end applications. The official device specifications can be found in the Si5386

datasheet.

The Si5386 is a high-performance, clock generator for small cell applications that de-

mand the highest level of integration and phase noise performance. Based on Silicon

Laboratories' fourth-generation DSPLL technology, the Si5386 combines frequency syn-

thesis and jitter attenuation in a highly integrated digital solution. A single low phase

noise XO connected to the XA/XB input pins provides the reference for the device. This

all-digital solution provides superior performance that is highly immune to external board

disturbances such as power supply noise.The device configuration is in-circuit program-

mable via an SPI or I

C serial interface and is easily stored in non-volatile memory

(NVM) for applications which require preconfigured clocks at start-up or after reset.

Work Flow Expectations with ClockBuilder

This reference manual is to be used to describe all the functions and features of the

parts in the product family with register map details on how to implement them. It is im-

portant to understand that the intent is for customers to use the ClockBuilder

ware to provide the initial configuration for the device. Although the register map is docu-

mented, all the details of the algorithms to implement a valid frequency plan are fairly

complex and are beyond the scope of this document. Real-time changes to the frequen-

cy plan and other operating settings are supported by the devices. However, describing

all the possible changes is not a primary purpose of this document. Refer to Applications

Notes and Knowledge Base article links within the ClockBuilder Pro GUI for information

on how to implement the most common, real-time frequency plan changes.

silabs.com | Building a more connected world.

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Pro and the Register Map

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Summary of Contents for Silicon Laboratories Si5386

Page 1 This Reference Manual is intended to provide system, PCB design, signal integrity, and software engineers the necessary technical information to successfully use the Si5386 RELATED DOCUMENTS device in end applications. The official device specifications can be found in the Si5386 datasheet. • Si5386 Data Sheet •...
Page 2: Table Of Contents
Table of Contents 1. Functional Description ......5 1.1 DSPLL ....... . 5 1.2 LTE Frequency Configuration .
Page 3 9. XO and Device Circuit Layout Recommendations....9.1 Si5386 64-Pin QFN External XO Layout Recommendations ....61 10.
Page 4 12.3 Page 2 Registers ......91 12.4 Page 3 Registers ......97 12.5 Page 4 Registers .
Page 5: Functional Description
Si5386. The ClockBuilder Pro software utility provides a simple means of automatically calculating the optimum divider values (P, M, N and R) for the frequencies listed below. In addition to the LTE frequencies, the Si5386 device can simultaneously gen- erate wireline clocks like 156.25 MHz, 155.52 MHz, 125 MHz, etc.
Page 6 Si5386 Rev. E Reference Manual Functional Description Table 1.1. Example List of Possible LTE Clock Frequencies LTE Device Clock Fout (MHz) 15.36 19.20 30.72 38.40 61.44 76.80 122.88 153.60 184.32 245.76 307.20 368.64 491.52 614.40 737.28 983.04 1228.80 1474.56 1638.4 1843.2...
Page 7: Configuration For Jesd204B Subclass 1 Clock Generation
(DCLK) and system reference clocks (SYSREF). The 12 clock outputs can be independently configured as device clocks or SYSREF clocks to drive JESD204B ADCs, DACs, FPGAs, or other logic devices. The Si5386 will clock up to six JESD204B subclass 1 targets, using six DCLK/SYSREF pairs.
Page 8: Dspll Loop Bandwidth
Si5386 Rev. E Reference Manual Functional Description 1.4 DSPLL Loop Bandwidth The DSPLL loop bandwidth determines the amount of input clock jitter attenuation and wander filtering. Register configurable DSPLL loop bandwidth settings in the range of 1 Hz to 4 kHz are available for selection. Since the loop bandwidth is controlled digitally, the DSPLL will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.
Page 9: Holdover Exit Bandwidth
Figure 1.1 Si5386 Block Diagram on page 7 shows all of these dividers. All divider values for the Si5386 may be either Fractional or Integer. For best phase noise performance, integer dividers are preferred.. • P0-P3: Input clock wide range dividers (0x0208–0x022F) •...
Page 10: Modes Of Operation
Si5386 Rev. E Reference Manual Modes of Operation 2. Modes of Operation After initialization, the DSPLL will operate in one of the following modes: Free-run, Lock-Acquisition, Locked, or Holdover. These modes are described further in the sections below. Power-Up Reset and...
Page 11: Reset And Initialization
Serial interface ready Figure 2.2. Initialization from Hard Reset and Soft Reset The Si5386 is fully configurable using the serial interface (I C or SPI). At power up the device downloads its default register values from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up.
Page 12: Updating Registers During Device Operation
Si5386 Rev. E Reference Manual Modes of Operation 2.1.1 Updating Registers During Device Operation If certain registers are changed while the device is in operation, it is possible for the PLL to become unresponsive (i.e. lose lock indefi- nitely). Any change that causes the VCO frequency to change by more than 250 ppm since Power-up, NVM download, or SOFT_RST requires the following special sequence of writes.
Page 13: Nvm Programming
Si5386 Rev. E Reference Manual Modes of Operation 2.1.2 NVM Programming The NVM is two-time writable by the user. Once a new configuration has been written to NVM, the old configuration is no longer acces- sible. While polling DEVICE_READY during the procedure below, the following conditions must be met in order to ensure that the correct values are written into the NVM: •...
Page 14: Holdover Mode
Si5386 Rev. E Reference Manual Modes of Operation 2.5 Holdover Mode The DSPLL will automatically enter Holdover mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. It uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the out- put clock phase and frequency when an input clock suddenly fails.
Page 15 Si5386 Rev. E Reference Manual Modes of Operation Table 2.3. Holdover Mode Control Registers Register Name Hex Address Function [Bit Field] Holdover Status HOLD 0x000E[5] DSPLL Holdover status indicator. 0: Normal Operation 1: In Holdover/Freerun Mode: HOLD_HIST_VALID = 0 ≥ Freerun Mode HOLD_HIST_VALID = 1 ≥...
Page 16 Si5386 Rev. E Reference Manual Modes of Operation Register Name Hex Address Function [Bit Field] HOLDEXIT_BW_SEL0 0x059B[6] Select the exit bandwidth from Holdover when ramped exit is not selected (HOLD_RAMP_BYP = 1). 00: Use Fastlock bandwidth on Holdover exit 01: Use Holdover Exit bandwidth on Holdover exit (default)
Page 17: Clock Inputs (In0, In1, In2, In3)
Si5386 Rev. E Reference Manual Clock Inputs (IN0, IN1, IN2, IN3) 3. Clock Inputs (IN0, IN1, IN2, IN3) 3.1 Input Source Selection The inputs accept both standard format inputs and DC coupled CMOS clocks. Input selection from CLK_SWITCH_MODE can be man- ual (pin or register controlled) or automatic with user definable priorities.
Page 18: Automatic Input Switching
Si5386 Rev. E Reference Manual Clock Inputs (IN0, IN1, IN2, IN3) 3.1.2 Automatic Input Switching In automatic mode CLK_SWITCH_MODE = 0x01 (Non-revertive) or 0x02 (Revertive). Automatic input switching is available in addition to the manual selection described previously in 3.1.1 Manual Input Selection.
Page 19: Types Of Inputs
Si5386 Rev. E Reference Manual Clock Inputs (IN0, IN1, IN2, IN3) 3.2 Types of Inputs Each of the four different inputs IN0-IN3/FB_IN can be configured as standard LVDS, LVPECL, HCL, CML, and AC-coupled single- ended LVCMOS formats, or as DC-coupled CMOS format. The standard format inputs have a nominal 50% duty cycle, must be ac- coupled and use the “Standard”...
Page 20: Hitless Input Switching With Phase Buildout
Si5386 Rev. E Reference Manual Clock Inputs (IN0, IN1, IN2, IN3) Input clock buffers are enabled by setting the IN_EN 0x0949[3:0] bits appropriately for IN3 through IN0. Unused clock inputs may be powered down and left unconnected at the system level. For standard mode inputs, both input pins must be properly connected as shown in the figure above, including the “Standard AC Coupled Single Ended”...
Page 21: Ramped Input Switching
Si5386 Rev. E Reference Manual Clock Inputs (IN0, IN1, IN2, IN3) 3.2.2 Ramped Input Switching The DSPLL has the ability to switch between two input clock frequencies that are up to ±20 ppm apart. When switching between input clocks that are not exactly the same frequency (i.e. are plesiochronous), ramped switching should be enabled to ensure a smooth tran- sition between the two input frequencies.
Page 22: Fault Monitoring
Si5386 Rev. E Reference Manual Clock Inputs (IN0, IN1, IN2, IN3) 3.3 Fault Monitoring The four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF). Note that the XAXB reference clock is also monitored for LOS since it provides a critical reference clock for the DSPLL. There is also a Loss of Lock (LOL) indicators asserted when the DSPLL loses synchronization within the feedback loop.
Page 23 Si5386 Rev. E Reference Manual Clock Inputs (IN0, IN1, IN2, IN3) Table 3.7. LOS Monitoring and Control Registers Register Name Hex Address Function [Bit Field] LOS Status and Controls 0x000D[3:0] LOS status indicators for IN3 - IN0. 0: Input signal detected or input buffer disabled or LOS dis-...
Page 24: Input Oof (Out-Of-Frequency) Detection
Si5386 Rev. E Reference Manual Clock Inputs (IN0, IN1, IN2, IN3) 3.3.3 Input OOF (Out-of-Frequency) Detection Each input clock is monitored for frequency accuracy with respect to an OOF reference which it considers as its 0 ppm reference. This OOF reference can be selected as either: •...
Page 25 Si5386 Rev. E Reference Manual Clock Inputs (IN0, IN1, IN2, IN3) Register Name Hex Address Function [Bit Field] OOF_INTR_MSK 0x0018[7:4] Masks OOF from generating INTRb interrupt for IN3 - IN0. 0: Allow OOF interrupt (default) 1: Mask (ignore) OOF for interrupt...
Page 26: Dspll Lol (Loss-Of-Lock) Detection And The Lolb Output Indicator Pin
÷M ÷5 Figure 3.6. Si5386 LOL Status Indicator The LOL frequency monitor has an adjustable sensitivity which is register-configurable from ±1 ppm to ±10,000 ppm. Having two sepa- rate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is indica- ted when there is less than 0.1 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there's more...
Page 27 Si5386 Rev. E Reference Manual Clock Inputs (IN0, IN1, IN2, IN3) Table 3.9. LOL Status Monitor and Control Registers Register Name Hex Address Function [Bit Field] 0x000E[1] LOL status indicator for the DSPLL. 0: DSPLL Locked to input clock 1: DSPLL Not locked to an input clock...
Page 28: Device Status Monitoring
Si5386 Rev. E Reference Manual Clock Inputs (IN0, IN1, IN2, IN3) 3.3.5 Device Status Monitoring In addition to the input-driven LOS, LOSXAXB, OOF, LOL, and HOLD fault monitors discussed previously, there are several additional status monitors which may be useful in determining the device operating state. While some of these indicators may seem redundant, they are either taken from different locations in the device or are active in different operating modes.
Page 29: Intrb Interrupt Configuration
Si5386 Rev. E Reference Manual Clock Inputs (IN0, IN1, IN2, IN3) Hex Address Register Name Function [Bit Field] CAL indicator sticky flag bit. Remains as- serted after the indicator bit shows a fault CAL_FLG 0x0014[5] until cleared by the user. Writing a 0 to the flag bit will clear it if the indicator bit is no longer asserted.
Page 30 Si5386 Rev. E Reference Manual Clock Inputs (IN0, IN1, IN2, IN3) Table 3.11. INTRb Pin Interrupt Mask Registers Register Name Hex Address Function [Bit Field] LOS_INTR_MSK 0x0018[3:0] Masks LOS from generating INTRb interrupt for IN3 - IN0. 0: Allow LOS interrupt (default)
Page 31: Output Clocks
Si5386 Rev. E Reference Manual Output Clocks 4. Output Clocks Each output driver has configurable output amplitude and common mode voltage, covering a wide variety of differential signal output formats including LVPECL, LVDS, HCSL, and CML. In addition to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3, 2.5, or 1.8V) providing up to 20 single-ended outputs or any combination of differential and single-...
Page 32: Output R Divider Synchronization
Si5386 Rev. E Reference Manual Output Clocks Table 4.1. Output Crosspoint Configuration Registers Register Name Hex Address Function [Bit Field] OUT0A_MUX_SEL 0x0106[2:0] Connects the output drivers to one of the N divider sources. Selections are: OUT0_MUX_SEL 0x010B[2:0] 0: N0 OUT1_MUX_SEL...
Page 33: Performance Guidelines For Outputs
Use of integer-related output frequencies reduces the opportunity for crosstalk as these frequencies are derived from the same output divider. However, the phase noise of the Si5386 is so low that crosstalk may still be detected in certain cases.
Page 34: Optimizing Output Phase Noise
4.2.1 Optimizing Output Phase Noise To obtain the best phase noise performance for RF and other demanding applications, it is important to configure the Si5386 device optimally. Using integer dividers for P, M, and N will provide the highest level of performance. Integer mode dividers are optimized to support LTE, JESD204b and other integer-ratio derived frequencies.
Page 35: Output Driver Supply Select
Si5386 Rev. E Reference Manual Output Clocks 4.4 Output Driver Supply Select The VDDO output driver voltage may be selected separately for each driver. The selected voltage must match the voltage supplied to that VDDO pin in the end system. VDDO pins for unused (unconnected) outputs can be left unconnected, or may be connected to a convenient 1.8 V–3.3 V system supply without increasing power dissipation.
Page 36: Differential Outputs
= 3.3V , 2.5V , 1.8V OUTx Standard HCSL OUTxb Receiver For V = 0.35V 3.3V 56. 2 2.5V 1.8V 63. 4 Figure 4.2. Si5386 Supported Differential Output Terminations silabs.com | Building a more connected world. Rev. 0.9 | 36...
Page 37: Differential Output Amplitude Controls
Si5386 Rev. E Reference Manual Output Clocks 4.5.2 Differential Output Amplitude Controls The differential amplitude of each output can be controlled with the following registers. See 4.5.4 Recommended Settings for Differen- tial LVPECL, LVDS, HCSL, and CML for recommended OUTx_AMPL settings for common signal formats. See 4.5.2 Differential Output...
Page 38: Recommended Settings For Differential Lvpecl, Lvds, Hcsl, And Cml
2. Creates HCSL compatible signals, see HCSL receiver biasing network in Figure 4.2 Si5386 Supported Differential Output Termi- nations on page The output differential driver can also produce a wide range of CML compatible output amplitudes. See 13.
Page 39: Lvcmos Output Terminations
Si5386 Rev. E Reference Manual Output Clocks 4.6.1 LVCMOS Output Terminations LVCMOS outputs are dc-coupled as shown in the following figure. DC Coupled LVCMOS 3.3V, 2.5V, 1.8V LVCMOS = 3.3V, 2.5V, 1.8V OUTx OUTxb Figure 4.3. LVCMOS Output Terminations silabs.com | Building a more connected world.
Page 40: Lvcmos Output Impedance And Drive Strength Selection
Si5386 Rev. E Reference Manual Output Clocks 4.6.2 LVCMOS Output Impedance and Drive Strength Selection Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A series source termination resistor (Rs) is recommended close to the output to match the selected output impedance to the trace impedance (i.e.
Page 41: Lvcmos Output Polarity
Si5386 Rev. E Reference Manual Output Clocks 4.6.4 LVCMOS Output Polarity When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUT and OUTb). By default the clock on the OUTb pin is generated with the same polarity (in phase) with the clock on the OUT pin. The polarity of these clocks is configurable enabling complimentary clock generation and/or inverted polarity with respect to other output drivers.
Page 42: Output Enable/Disable
Si5386 Rev. E Reference Manual Output Clocks 4.7 Output Enable/Disable Each output driver may be individually placed in one of three operating states: • “Enabled” state is the normal state for output clock operation. The output clock is toggling and the differential common mode voltage will be generated, if selected by the output format.
Page 43: Output Driver State When Disabled
Si5386 Rev. E Reference Manual Output Clocks 4.7.1 Output Driver State When Disabled The disabled state of an output driver is configurable as: disable logic low or disable logic high. Table 4.13. Output Driver Disable State Registers Register Name Hex Address...
Page 44: Automatic Output Disable During Lol
Si5386 Rev. E Reference Manual Output Clocks 4.7.3 Automatic Output Disable During LOL By default, a DSPLL that is out of lock will generate an output clock. There is an option to disable the outputs when the DSPLL is out of lock (LOL).
Page 45: Output Driver Disable Source Summary
Si5386 Rev. E Reference Manual Output Clocks 4.7.5 Output Driver Disable Source Summary There are a number of conditions that may cause the outputs to be automatically disabled. The user may mask out unnecessary disa- ble sources to match system requirements. Any one of the unmasked sources may cause the output(s) to be disabled; this is more powerful, but similar in concept, to common “wired-OR”...
Page 46: Output Delay Control
4.8 Output Delay Control The Si5386 uses independently adjustable output N dividers (N0 - N4) to generate up to 5 unique top frequencies to its 12 outputs through the output crosspoint switch. By default all output clocks are aligned. Each N divider has an independently adjustable delay path (Δt0 –...
Page 47: Zero Delay Mode
This helps to cancel out internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. The OUT9A output and FB_IN input should be used for the external feedback connection in the Si5386 to minimize the overall distance and delay.
Page 48 Si5386 Rev. E Reference Manual Zero Delay Mode Table 5.1. Zero Delay Mode Registers Register Name Hex Address [Bit Field] Function OUTX_ALWAYS_ON 0x013F[7:0] Force ZDM output always on. 0x0140[3:0] 0x000: Do not force output on (default) 0x800: Force OUT9A always on for ZDM...
Page 49: Serial Interface
I C or SPI operation. The Si5386 supports communication with a 3.3 V or 1.8 V host by setting the IO_VDD_SEL (0x0943[0]) configuration bit. The SPI interface supports both 4-wire or 3-wire modes by setting the SPI_3WIRE (0x002B[3]) configuration bit. See the figure below for supported modes of operation and settings.
Page 50 Si5386 Rev. E Reference Manual Serial Interface The following table lists register settings of interest for the I C/SPI serial interface operation. Table 6.1. I2C/SPI Configuration Registers Register Name Hex Address [Bit Field] Function IO_VDD_SEL 0x0943[0] Select digital I/O operating voltage.
Page 51: I 2 C Interface
C Configuration The 7-bit I C slave device address of the Si5386 consists of a 5-bit fixed address plus two bit determined by the voltages on the A1 and A0 input pins, as shown in the figure below. Slave Address Figure 6.3.
Page 52 Si5386 Rev. E Reference Manual Serial Interface Write Operation – Single Byte Slv Addr [6:0] A Reg Addr [7:0] Data [7:0] Write Operation - Burst (Auto Address Increment) Slv Addr [6:0] A Reg Addr [7:0] Data [7:0] Data [7:0] Reg Addr +1 1 –...
Page 53: Spi Interface
Si5386 Rev. E Reference Manual Serial Interface 6.2 SPI Interface When in SPI mode, the serial interface operates in 4-wire or 3-wire depending on the state of the SPI_3WIRE configuration bit, 0x000B[3]. The 4-wire interface consists of a clock input (SCLK), a chip select input (CSb), serial data input (SDI), and serial data out- put (SDO).
Page 54 Si5386 Rev. E Reference Manual Serial Interface ‘Set Address’ and ‘Write Data’ ‘Set Addr’ Addr [7:0] ‘Write Data’ Data [7:0] ‘Set Addr’ Addr [7:0] ‘Write Data’ Data [7:0] ‘Set Addr’ Addr [7:0] ‘Write Data’ Data [7:0] ‘Set Address’ and ‘Write Data + Address Increment’...
Page 55 Si5386 Rev. E Reference Manual Serial Interface Previous Next ‘Set Address’ Command Command Command >1.9 2 Cycle SCLK Wait Periods Set Address Instruction Base Address SCLK 4-Wire 3-Wire SDIO High Impedance Host Clock IC Don’t Care Host Clock IC Figure 6.9. SPI "Set Address" Command Timing silabs.com | Building a more connected world.
Page 56 Si5386 Rev. E Reference Manual Serial Interface Previous Next ‘Write Data’ Command Command >1.9 2 Cycle SCLK Data byte @ base address Wait Periods Write Data instruction Data byte @ base address + 1 SCLK 4-Wire 3-Wire SDIO High Impedance...
Page 57 Si5386 Rev. E Reference Manual Serial Interface Previous Next ‘Read Data’ Command Command >1.9 2 Cycle SCLK Read byte @ base address Wait Periods Read Data instruction Read byte @ base address + 1 SCLK 4-Wire 3-Wire SDIO Don’t Care...
Page 58: Field Programming
7. Field Programming To simplify design and software development of systems using the Si5386, a field programmer is available. The ClockBuilder Pro Field Programmer supports both “in-system” programming for devices already mounted on a PCB, as well as “in-socket” programming of Si5386 sample devices.
Page 59: Xaxb External References
The Si5386 accepts a Clipped Sine wave, CMOS, or Differential reference clock on the XAXB interface. Most clipped sine wave and CMOS XOs have insufficient drive strength to drive a 50 Ω or 100 Ω load. For this reason, place the XO as close to the Si5386 as possible to minimize PCB trace length.
Page 60: Recommended Reference Oscillators
8.2 Recommended Reference Oscillators The Si5386 can use either 54 MHz or 48.0231 MHz reference XOs. This should be a high-quality “low phase noise” or “ultra-low phase noise” type to reduce phase noise on the output clocks. See the table below for a list of some recommended XOs to use with this de- vice.
Page 61: Xo And Device Circuit Layout Recommendations
• Layer 8: ground layer External XO: The figure below shows the top layer layout of the Si5386 device mounted on the PCB. The XO is outlined with the white box around it. The top layer is flooded with ground. Both the XA and XB pins are capacitively coupled, with XB ac connected to XO ground for single-ended output XO's.
Page 62 Si5386 Rev. E Reference Manual XO and Device Circuit Layout Recommendations External XO: The following figure shows the layer that implements the ground shield underneath the XO. This layer also has the clock input pins. The clock input pins go to layer 2 using vias to avoid crosstalk. As soon as the clock inputs are on layer 2, they have a ground shield above, below, and on the sides for maximum protection.
Page 63 Si5386 Rev. E Reference Manual XO and Device Circuit Layout Recommendations External XO: The figure below shows one of the ground planes. Figure 9.4 External XO: Internal Power Plane (Layer 4) on page 63 a power plane and shows the clock output power supply traces.
Page 64 Si5386 Rev. E Reference Manual XO and Device Circuit Layout Recommendations External XO: The figure below shows layer 5, which is the power plane routed to the clock output power pins. Figure 9.5. External XO: Internal Power Plane (Layer 5) External XO: The figure below shows layer 6, another ground plane similar to layer 3.
Page 65 Si5386 Rev. E Reference Manual XO and Device Circuit Layout Recommendations External XO: The figure below shows the output clocks. Similar to the input clocks, the output clocks have vias that immediately go to a buried layer with a ground plane above them and a ground flooded bottom layer. There is ground flooding between the clock output pairs to reduce crosstalk.
Page 66 Si5386 Rev. E Reference Manual XO and Device Circuit Layout Recommendations External XO: The bottom layer shown in the figure below displays the location of the decoupling capacitors close to the device. Figure 9.8. External XO: Bottom Layer Ground Flooded (Layer 8) silabs.com | Building a more connected world.
Page 67: Power Management
10.2 Power Supply Recommendations Power supply filtering is generally important for optimal timing performance. The Si5386 devices have multiple stages of on-chip regula- tion to minimize the impact of board level noise on clock jitter. Following conventional power supply filtering and layout techniques will minimize signal degradation from power supply noise.
Page 68: Power Supply Sequencing
Si5386 Rev. E Reference Manual Power Management 10.3 Power Supply Sequencing Four classes of supply voltages exist on the Si5386: 1. VDD = 1.8 V (Core digital supply) 2. VDDA = 3.3 V (Analog supply) 3. VDDO = 1.8/2.5/3.3 V (Output Clock supplies) There is no general requirement for power supply sequencing on this device unless the output clocks are required to be phase aligned with each other.
Page 69: Base Vs. Factory Preprogrammed Devices
ClockBuilder Pro project file. • Si5386A-E-GM: Applies to a "base" device. Base devices are factory programmed to a specific base part type (e.g., Si5386) but exclude any user-defined frequency plan or other operating characteristics which would be selected in ClockBuilder Pro.
Page 70: Register Map
Si5386 Rev. E Reference Manual Register Map 12. Register Map 12.1 Page 0 Registers Table 12.1. Register 0x0000 Die Rev Reg Address Bit Field Type Name Default Description 0x0000 DIE_REV 4-bit die revision number Table 12.2. Register 0x0001 Page Reg Address...
Page 71 Si5386 Rev. E Reference Manual Register Map 11.3 Part Numbering Summary for more information on part numbers. Refer to the device data sheet Ordering Guide section for more information about device grades. Table 12.6. Register 0x0009 Temperature Grade Reg Address...
Page 72 Si5386 Rev. E Reference Manual Register Map 3.3 Fault Monitoring for more information. • IN0: LOS 0x000D[0], OOF 0x000D[4] • IN1: LOS 0x000D[1], OOF 0x000D[5] • IN2: LOS 0x000D[2], OOF 0x000D[6] • IN3/FB_IN: LOS 0x000D[3], OOF 0x000D[7] Table 12.11. Register 0x000E Holdover (HOLD) and Loss-of-Lock (LOL) Status...
Page 73 Si5386 Rev. E Reference Manual Register Map Table 12.15. Register 0x0013 HOLD and LOL Status Flags Reg Address Bit Field Type Name Description 0x0013 LOL_FLG Flag 1 if the DSPLL was or is LOL 0x0013 HOLD_FLG Flag 1 if the DSPLL was or is in Holdover or Freerun These are sticky flag bits corresponding to the bits in register 0x000E.
Page 74 Si5386 Rev. E Reference Manual Register Map Table 12.19. Register 0x0019 HOLD and LOL Interrupt Masks Reg Address Bit Field Type Name Description 0x0019 LOL_INTR_MSK 1 to mask LOL_FLG from causing an interrupt 0x0019 HOLD_INTR_MSK 1 to mask HOLD_FLG from caus- ing an interrupt These are interrupt mask bits corresponding to the bits in register 0x0013.
Page 75 Si5386 Rev. E Reference Manual Register Map Table 12.23. Register 0x0022 Output Enable Group Controls Reg Address Bit Field Type Name Description 0x0022 OE_REG_SEL Selects between Pin and Register control for output disable. 0: OEb Pin disable (default) 1: OE Register disable...
Page 76 Si5386 Rev. E Reference Manual Register Map Table 12.26. Register 0x002D LOS Clear Delays Reg Address Bit Field Type Name Description 0x002D LOS0_VAL_TIME IN0 LOS Clear delay. 0: 2 ms 1: 100 ms 2: 200 ms 3: 1000 ms 0x002D...
Page 77 Si5386 Rev. E Reference Manual Register Map Table 12.30. Register 0x003E LOS Min Period Enable Reg Address Bit Field Type Name Description 0x003E LOS_MIN_PERI- Values set by CBPro. OD_EN Table 12.31. Register 0x003F OOF Enable Reg Address Bit Field Type...
Page 78 Si5386 Rev. E Reference Manual Register Map Table 12.35. Register 0x0043 OOF2 Divider Select Reg Address Bit Field Type Name Description 0x0043 OOF2_DIV_SEL Values calculated by CBPro. Table 12.36. Register 0x0044 OOF3 Divider Select Reg Address Bit Field Type Name...
Page 79 Si5386 Rev. E Reference Manual Register Map Table 12.41. Register 0x0050 OOF on LOS Controls Reg Address Bit Field Type Name Description 0x0050 OOF_ON_LOS Values set by CBPro. Table 12.42. Register 0x0051-0x0054 Fast OOF Set Thresholds Reg Address Bit Field...
Page 80 Si5386 Rev. E Reference Manual Register Map Table 12.46. Register 0x005E–0x061 OOF1 Ratio for Reference Reg Address Bit Field Type Name Description 0x005E OOF1_RATIO_REF 0x005F 15:8 OOF1_RATIO_REF Values calculated by CBPro 0x0060 23:16 OOF1_RATIO_REF 0x0061 25:24 OOF1_RATIO_REF Table 12.47. Register 0x0062–0x065 OOF2 Ratio for Reference...
Page 81 Si5386 Rev. E Reference Manual Register Map Table 12.52. Register 0x0096 Fast LOL Set Threshold Reg Address Bit Field Type Name Description 0x0096 LOL_FST_SET_THR_SEL Values calculated by CBPro Table 12.53. Register 0x0098 Fast LOL Clear Threshold Reg Address Bit Field...
Page 82 Si5386 Rev. E Reference Manual Register Map • 6 = ±100 ppm • 7 = ±300 ppm • 8 = ±1000 ppm • 9 = ±3000 ppm • 10 = ±10000 ppm • 11–15: Reserved Table 12.59. Register 0x00A2 LOL Timer Enable...
Page 83 Si5386 Rev. E Reference Manual Register Map Table 12.63. Register 0x00E4 Read Active NVM Bank Reg Address Bit Field Type Name Description 0x00E4 NVM_READ_BANK Set to 1 to initiate NVM copy to registers. Table 12.64. Register 0x00E5 Fastlock Extend Enable...
Page 84: Registers
Si5386 Rev. E Reference Manual Register Map 12.2 Page 1 Registers Table 12.67. Register 0x0102 Global Output Gating for all Clock Outputs Reg Address Bit Field Type Name Description 0x0102 OUTALL_DISABLE_LOW Enable/Disable All output drivers. If the OEb pin is held high, then all outputs will be disabled regardless of this setting.
Page 85 Si5386 Rev. E Reference Manual Register Map Table 12.69. Register 0x0104 OUT0A Output Format and Configuration Reg Address Bit Field Type Name Description 0x0104 OUT0A_FORMAT Select output format. 0: Reserved 1: Differential Normal mode 2: Differential Low-Power mode 3: Reserved...
Page 86 Si5386 Rev. E Reference Manual Register Map ClockBuilder Pro is used to select the correct settings for this register. See Table 4.7 Recommended Settings for Differential LVPECL, LVDS, HCSL, and CML on page 38 13. Appendix—Custom Differential Amplitude Controls for details of the settings.
Page 87 Si5386 Rev. E Reference Manual Register Map Table 12.73. Output Registers Following the Same Definitions as OUT0A Register Address Description (Same as) Address 0x0108 OUT0 Powerdown, Output Enable, 0x0103 and R0 Divide-by-2 0x0109 OUT0 Signal Format and Configura- 0x0104 tion...
Page 88 Si5386 Rev. E Reference Manual Register Map Register Address Description (Same as) Address 0x011F OUT4 Source Selection and 0x0106 LVCMOS Inversion 0x0120 OUT4 Disable Source 0x0107 0x0121 OUT5 Powerdown, Output Enable, 0x0103 and R5 Divide-by-2 0x0122 OUT5 Signal Format and Configura-...
Page 89 Si5386 Rev. E Reference Manual Register Map Register Address Description (Same as) Address 0x0138 OUT9 Source Selection and 0x0106 LVCMOS Inversion 0x0139 OUT9 Disable Source 0x0107 0x013A OUT9A Powerdown, Output Enable, 0x0103 and R9A Divide-by-2 0x013B OUT9A Signal Format and Configu-...
Page 90 Si5386 Rev. E Reference Manual Register Map Table 12.76. Register 0x0142 Output Disable Mask for LOL Reg Address Bit Field Type Name Description 0x0142 OUT_DIS_MASK_LOL Mask LOL from disabling all output drivers. 0: Disable All output drivers on LOL (default)
Page 91 Si5386 Rev. E Reference Manual Register Map 12.3 Page 2 Registers Table 12.78. Register 0x0208-0x020D P0 Divider Numerator Reg Address Bit Field Type Name Description 0x0208 P0_NUM 48-bit Integer Number 0x0209 15:8 0x020A 23:16 0x020B 31:24 0x020C 39:32 0x020D 47:40 Table 12.79.
Page 92 Si5386 Rev. E Reference Manual Register Map Table 12.82. Register 0x0231 P0 Factional Division Enable Reg Address Bit Field Type Name Description 0x0231 P0_FRACN_MODE P0 (IN0) input divider fractional mode. Must be set to 0xB for proper operation. 0x0231 4 R/W P0_FRAC_EN P0 (IN0) in- put divider fractional enable.
Page 93 Si5386 Rev. E Reference Manual Register Map Table 12.86. Register 0x0235–0x023A MXAXB Divider Numerator Reg Address Bit Field Type Name Description 0x0235 MXAXB_NUM 0x0236 15:8 MXAXB_NUM 0x0237 23:16 MXAXB_NUM 44-bit Integer Number 0x0238 31:24 MXAXB_NUM 0x0239 39:32 MXAXB_NUM 0x023A 47:40...
Page 94 Si5386 Rev. E Reference Manual Register Map Table 12.90. Registers that Follow the R0A_REG Register Address Description Size Same as Address 0x024A-0x024C R0_REG 24-bit Integer Number 0x0247-0x0249 0x024D-0x024F R1_REG 24-bit Integer Number 0x0247-0x0249 0x0250-0x0252 R2_REG 24-bit Integer Number 0x0247-0x0249 0x0253-0x0255...
Page 95 Si5386 Rev. E Reference Manual Register Map Table 12.92. Register 0x0278–0x027C OPN Identifier Reg Address Bit Field Type Name Description 0x0278 OPN_ID0 OPN unique identifier. ASCII enco- ded. For example, with OPN: 0x0279 15:8 OPN_ID1 Si5386A-E12345-GM, 12345 is the 0x027A...
Page 96 Si5386 Rev. E Reference Manual Register Map Table 12.97. Register 0x0294 Fastlock Extend Scale Reg Address Bit Field Type Name Description Value calculated in CBPro based on pa- 0x0294 FASTLOCK_EXTEND_SCL rameter selected. Table 12.98. Register 0x0296 Fastlock Delay on Input Switch...
Page 97 Si5386 Rev. E Reference Manual Register Map 12.4 Page 3 Registers Table 12.104. Register 0x0302-0x0307 N0 Numerator Reg Address Bit Field Type Name Description 0x0302 N0_NUM N Output Divider Numerator. 44-bit Integer. 0x0303 15:8 0x0304 23:16 0x0305 31:24 0x0306 39:32...
Page 98 Si5386 Rev. E Reference Manual Register Map Register Address Description Size Same as Address 0x0334-0x0337 N4_DEN 32-bit Integer 0x0308-0x030B 0x0338 N4_UPDATE one bit 0x030C Table 12.108. Register 0x0338 Global N Divider Update Reg Address Bit Field Type Name Description 0x0338...
Page 99 Si5386 Rev. E Reference Manual Register Map N3_DELAY behaves in the same manner as N0_DELAY above. Table 12.113. Register 0x0361-0x0362 N4 Delay Control Reg Address Bit Field Type Name Description 0x0361-0x0362 N4_DELAY[15:8] 8.8-bit, 2s-complement delay for N4_DELAY behaves in the same manner as N0_DELAY above.
Page 100 Si5386 Rev. E Reference Manual Register Map 12.6 Page 5 Registers Table 12.115. Register 0x0507 DSPLL Active Input Indicator Reg Address Bit Field Type Name Description 0x0507 IN_ACTV Currently selected DSPLL input clock. 0: IN0 1: IN1 2: IN2 3: IN3/FB_IN This register displays the currently selected input for the DSPLL.
Page 101 Si5386 Rev. E Reference Manual Register Map Table 12.118. Register 0x0514 DSPLL Bandwidth Update Reg Address Bit Field Type Name Description 0x0514 BW_UPDATE Set to 1 to latch updated bandwidth registers into operation. Setting this self-clearing bit high latches all of the new DSPLL bandwidth register values into operation. Asserting this strobe will update all of the BWx_PLL, FASTLOCK_BWx_PLL, and HOLDEXIT_BWx bandwidths at the same time.
Page 102 Si5386 Rev. E Reference Manual Register Map Table 12.122. Register 0x0521 PLL M Divider Fractional Enable Reg Address Bit Field Type Name Description 0x0521 M_FRAC_MODE M feedback divider frac- tional mode. Must be set to 0x0B for proper operation 0x0521...
Page 103 Si5386 Rev. E Reference Manual Register Map Table 12.125. Register 0x052C Holdover Exit Control Reg Address Bit Field Type Name Description 0x052C HOLD_EN Holdover enable 0: Holdover Disabled 1: Holdover Enabled (default) 0x052C HOLD_RAMP_BYP Must be set to 1 for Normal Operation.
Page 104 Si5386 Rev. E Reference Manual Register Map Table 12.128. Register 0x0532-0x0534 Holdover Cycle Count Reg Address Bit Field Type Name Description 0x0532 HOLD_15M_CYC_COUNT 0x0533 15:8 HOLD_15M_CYC_COUNT Value calculated in CBPro. 0x0534 23:16 HOLD_15M_CYC_COUNT Table 12.129. Register 0x0535 Force Holdover Reg Address...
Page 105 Si5386 Rev. E Reference Manual Register Map Reg Address Bit Field Type Name Description 0x0537 IN_OOF_MSK Determines the OOF status for IN3 - IN0 and is used in determining a valid clock for the automatic input selection. 0: Use OOF in the automatic clock...
Page 106 Si5386 Rev. E Reference Manual Register Map Table 12.136. Register 0x053E Hitless Switching Length Reg Address Bit Field Type Name Description 0x053E HSW_COARSE_PM_DLY Value calculated in CBPro. Table 12.137. Register 0x053F DSPLL Hold Valid and Fastlock Status Reg Address Bit Field...
Page 107 Si5386 Rev. E Reference Manual Register Map Table 12.141. Register 0x059B Holdover Exit Reg Address Bit Field Type Name Description 0x059B INIT_LP_CLOSE_HO PLL acquisition method for Freerun to Lock transition. 0: Normal loop closure 1: Holdover exit ramp (default) 0x059B...
Page 108 Si5386 Rev. E Reference Manual Register Map Table 12.143. Register 0x059D-0x05A2 DSPLL Holdover Exit Bandwidth Reg Address Bit Field Type Name Description 0x059D HOLDEXIT_BW0 DSPLL Holdover Exit bandwidth parameters calculated by CBPro 0x059E HOLDEXIT_BW1 when ramp switching is disabled. 0x059F...
Page 109 Si5386 Rev. E Reference Manual Register Map Table 12.148. Register 0x05AD - 0x05AE Configuration Reg Address Bit Field Type Name Description 0x05AD OUT_MAX_LIMIT_LMT Set by CBPro. 0x05AE 15:0 Table 12.149. Register 0x5B1 - 0x05B2 Configuration Reg Address Bit Field Type...
Page 110 When the I C or SPI host is operating at 3.3V and the Si5386 at VDD=1.8V, the host must write IO_VDD_SEL=1. This will ensure that both the host and the serial interface are operating with the optimum signal thresholds.
Page 111 Si5386 Rev. E Reference Manual Register Map Table 12.154. Register 0x094E–0x094F Input Clock Buffer Hysteresis Reg Address Bit Field Type Name Description 0x094E REFCLK_HYS_SEL Value calculated in CBPro. 0x094F REFCLK_HYS_SEL Table 12.155. Register 0x094F Input CMOS Threshold Select Reg Address...
Page 112 Si5386 Rev. E Reference Manual Register Map 12.8 Page A Registers Table 12.156. Register 0x094A Enable N-divider 0.5x Reg Address Bit Field Type Name Description 0x0A02 N_ADD_0P5 Value calculated in CBPro. Table 12.157. Register 0x0A03 Output N Divider to Output Driver...
Page 113 Si5386 Rev. E Reference Manual Register Map Table 12.161. Register 0x0A1A Output N1 Divider Auto-Disable Reg Addresss` Bit Field Type Name Description 0x0A1A N1_LOAD_AUTO_DIS Set by CBPro Table 12.162. Register 0x0A20 Output N2 Divider Auto-Disable Reg Addresss` Bit Field Type...
Page 114 Si5386 Rev. E Reference Manual Register Map 12.9 Page B Registers Table 12.165. Register 0x0B24 Reserved Control Reg Address Bit Field Type Name Description 0x0B24 RESERVED Reserved This register is used when making certain changes to the device. See 2.1.1 Updating Registers During Device Operation for more infor- mation.
Page 115 Si5386 Rev. E Reference Manual Register Map Table 12.169. Register 0x0B46 Loss of Signal Clock Disables Reg Address Bit Field Type Name Description 0x0B46 LOS_CLK_DIS Disables LOS clock for IN3 - IN0. Must be set to 0 to enable the LOS function of the respective inputs.
Page 116 Si5386 Rev. E Reference Manual Register Map Table 12.174. Register 0x0B57-0x0B58 VCO Calcode Reg Address Bit Field Type Name Description 0x0B57 VCO_RESET_CALCODE Value calculated in CBPro. 0x0B58 VCO_RESET_CALCODE 12.10 Page C Registers Table 12.175. Register 0x0C02 Clock Validation Configuration Reg Address...
Page 117 Si5386 Rev. E Reference Manual Appendix—Custom Differential Amplitude Controls 13. Appendix—Custom Differential Amplitude Controls In some customer applications, it may be desirable to have larger or smaller differential amplitudes than those produced by the stand- ard LVPECL and LVDS settings generated by ClockBuilder Pro. For example, "CML" format is sometimes desired for an application, but CML is not a defined standard, and, hence, the input amplitude of CML signals may differ between receivers.
Page 118 Si5386 Rev. E Reference Manual Revision History 14. Revision History Revision 0.9 January, 2018 • Updated 2.1.2 NVM Programming. Revision 0.1 September, 2017 • Initial release. silabs.com | Building a more connected world. Rev. 0.9 | 118...
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