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Silego GreenPAK SLG46140 Manual

Programmable mixed-signal matrix
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General Description
The SLG46140 GreenPAK is a one-time non-volatile memory
(NVM) Programmable Mixed-Signal Matrix designed to
implement a wide variety of mixed-signal functions in a single,
small, low-power device by integrating a number of common
discrete ICs and passive components.
Features
• Logic & Mixed Signal Circuits
• Highly Versatile Macrocells
• 1.8V (±5%) to 5V (±10%) Supply
• Operating Temperature Range: -40°C to 85°C
• RoHS Compliant / Halogen-Free
• Pb-Free: 1.6 x 2.0 x 0.55 mm, 0.4 mm pitch
Applications
The extensive list of integrated components included in the SLG46140 can be used to implement these and many other
functions, often in combination.
•
Ambient Light Detect
•
Battery Charge Control
•
Fan Control
•
Hall Effect Drive
•
LED Control
•
Level Shift
•
One-Shot Detect
•
Optical Encode
•
Over Voltage Protect
Silego Technology, Inc.
000-0046140-111
Programmable Mixed-signal Matrix
Pin Configuration
VDD
GPI
GPIO
GPIO
GPIO
•
Port Detection
•
Power Sequencing
•
Sensor Interface
•
Signal De-Glitch
•
Signal Delay
•
System Reset
•
Thermal Management
•
Voltage Level Detect
SLG46140
GreenPAK
GPIO
1
12
14
13
GPIO
2
11
GPIO
3
10
GPIO
4
9
6
7
GND
5
8
14-pin STQFN
(Top View)
Rev 1.11
Revised March 16, 2018

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Summary of Contents for Silego GreenPAK SLG46140

  • Page 1 Signal De-Glitch • LED Control • Signal Delay • Level Shift • System Reset • One-Shot Detect • Thermal Management • Optical Encode • Voltage Level Detect • Over Voltage Protect Silego Technology, Inc. Rev 1.11 000-0046140-111 Revised March 16, 2018...

  • Page 2: Block Diagram

    SLG46140 Block Diagram Pin 14 Pin 13 GPIO GPIO Look Up Tables (LUTs) DAC0 ACMP0 ACMP1 2-bit 2-bit 2-bit LUT2_2 LUT2_0 LUT2_1 2-bit 3-bit 3-bit Pin 1 Pin 12 DAC1 LUT2_3 LUT3_0 LUT3_1 GPIO Additional Logic Functions 3-bit 3-bit LUT3_3 LUT3_2 FILTER_0 8-bit SAR...
  • Page 3 SLG46140 1.0 Overview In addition to the integrated analog and digital components, the SLG46140 comprises an internal connection matrix and one-time programmable NVM. By programming the NVM, using the easy-to-use GreenPAK development tools, the designer configures the connection matrix, I/O Pins, and integrated components of the SLG46140. The SLG46140 includes the following analog and digital resources: •...

  • Page 4: Pin Description

    SLG46140 2.0 Pin Description 2.1 Functional Pin Description Pin # Pin Name Function Power Supply General Purpose Input GPIO General Purpose I/O or ADC Vref_IO GPIO General Purpose I/O or Analog Comparator 0 (-) / PGA_OUT GPIO General Purpose I/O or Analog Comparator 1 (-) GPIO General Purpose I/O or PGA(+) GPIO...

  • Page 5: User Programmability

    Once the design is finalized, the programming code (.gpx file) is forwarded to Silego to integrate into a production process. Figure 1. Steps to create a custom Silego GreenPAK device...

  • Page 6: Ordering Information

    SLG46140 4.0 Ordering Information Part Number Type SLG46140V 14-pin STQFN SLG46140VTR 14-pin STQFN - Tape and Reel (3k units) 000-0046140-111 Page 5 of 169...

  • Page 7: Electrical Specifications

    SLG46140 5.0 Electrical Specifications 5.1 Absolute Maximum Conditions Parameter Min. Max. Unit Supply voltage on VDD relative to GND -0.5 DC Input voltage GND - 0.5 VDD + 0.5 Single-ended 1.98/G Differential (1.98 - 0.55)/G PGA Input voltage* Pseudo- (1.98 - 0.18)/G differential Push-Pull 1x Push-Pull 2x...
  • Page 8 SLG46140 Symbol Parameter Condition/Note Min. Typ. Max. Unit Vin = 0 V 0.39 2.39 ACMP Input Leakage Vin = VDD 0.26 1.29 Vin = 0 V 0.04 0.18 PGA Input Leakage Vin = VDD 0.12 0.65 Vin = 0 V 0.04 0.34 Logic Input without Schmitt...
  • Page 9 SLG46140 Symbol Parameter Condition/Note Min. Typ. Max. Unit Maximum Average or DC = 85°C Current Through VDD Pin = 110°C (Per chip side, see Note 2) Maximum Average or DC = 85°C Current Through GND Pin = 110°C (Per chip side, see Note 2) Maximal Voltage Applied to any PIN in High- Impedance State...
  • Page 10 SLG46140 5.3 Electrical Characteristics (3.3V ±10% V Symbol Parameter Condition/Note Min. Typ. Max. Unit Supply Voltage Static Inputs and Outputs (when all macrocells that require A Quiescent Current 0.16 internal RC OSC or bandgap are inactive) Operating Temperature °C Programming Voltage 7.25 7.50 7.75...
  • Page 11 SLG46140 Symbol Parameter Condition/Note Min. Typ. Max. Unit Push-Pull 1X, 0.151 0.280 = 3 mA Push-Pull 2X, 0.079 0.130 = 3 mA Push-Pull 4X, 0.055 0.104 = 3 mA LOW-Level Output Voltage Open Drain NMOS 1X, 0.070 0.130 = 3 mA Open Drain NMOS 2X, 0.040 0.070...
  • Page 12 SLG46140 Symbol Parameter Condition/Note Min. Typ. Max. Unit 1 M Pull Down 662.60 1074.47 1285.21 kΩ PDWN Pull Down Resistance 100 k Pull Down 92.42 110.60 132.48 kΩ 10 k Pull Down 10.00 11.88 14.25 kΩ Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides.
  • Page 13 SLG46140 5.4 Electrical Characteristics (5V ±10% V Symbol Parameter Condition/Note Min. Typ. Max. Unit Supply Voltage Static Inputs and Outputs (when all macrocells that require A Quiescent Current 0.25 internal RC OSC or bandgap are inactive) Operating Temperature °C Programming Voltage 7.25 7.50 7.75...
  • Page 14 SLG46140 Symbol Parameter Condition/Note Min. Typ. Max. Unit Push-Pull 1X, 0.193 0.330 = 5 mA Push-Pull 2X, 0.101 0.160 = 5 mA Push-Pull 4X, 0.071 0.135 = 5 mA LOW-Level Output Voltage Open Drain NMOS 1X, 0.090 0.160 = 5 mA Open Drain NMOS 2X, 0.050 0.080...
  • Page 15 SLG46140 Symbol Parameter Condition/Note Min. Typ. Max. Unit 1 M Pull Down 667.10 1074.89 1287.81 kΩ PDWN Pull Down Resistance 100 k Pull Down 92.03 110.34 132.21 kΩ 10 k Pull Down 9.45 11.55 14.05 kΩ Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides.
  • Page 16 SLG46140 5.5 Typical Delay Estimated for Each Macrocell Table 1. Typical Delay Estimated for Each Macrocell VDD=1.8V VDD=3.3V VDD=5.0V Unit Symbol Parameter Note Falling Falling Rising Rising Falling Rising Delay LUT 2-bit 17.43 15.33 6.31 6.09 4.20 4.31 Delay LUT 2-bit (Shared with DFF/Latch) 21.53 20.67 8.13...
  • Page 17 SLG46140 VDD=1.8V VDD=3.3V VDD=5.0V Unit Symbol Parameter Note Falling Falling Rising Rising Falling Rising PDLY 1Cells delayed output Rising Delay 192.15 75.71 48.65 edge detect PDLY 1Cells delayed output Fall- Delay 195.73 76.60 49.42 ing edge detect Delay PDLY 1Cells Rising edge detect 31.32 12.33 8.65...
  • Page 18 SLG46140 VDD=1.8V VDD=3.3V VDD=5.0V Unit Symbol Parameter Note Falling Falling Rising Rising Falling Rising Width PDLY 1Cells Rising edge detect 344.67 153.27 111.95 Width PDLY 1Cells Falling edge detect 345.80 153.73 112.43 Width PDLY 2Cells Both edge detect 692.87 694.27 306.80 307.33 223.53...
  • Page 19 SLG46140 VDD=1.8V VDD=3.3V VDD=5.0V Unit Symbol Parameter Note Falling Falling Rising Rising Falling Rising Digital Input without Schmitt trigger Delay 37.83 33.03 14.14 13.54 9.93 9.67 -- 3-state 4x Digital Input without Schmitt trigger Delay 42.03 15.61 10.78 -- Push Pull Z to 1 Digital Input without Schmitt trigger Delay 36.09...
  • Page 20 SLG46140 5.6 Typical Current Consumption Table 2. Typical Current Consumption Note VDD = 1.8V VDD = 3.3V VDD = 5.0V Unit Quiescent current 0.08 0.16 0.25 Low frequency OSC; Clock predivider by 1 0.37 0.48 0.67 Low frequency OSC; Clock predivider by 16 0.36 0.46 0.64...
  • Page 21 SLG46140 5.7 OSC Specifications 5.7.1 25 kHz RC Oscillator Table 3. 25 kHz RC OSC frequency limits Temperature Range Power Supply Range +25 °C 0 °C ... +85 °C -40 °C ... +85 °C (VDD) V Minimum Maximum Minimum Maximum Minimum Maximum Value, kHz...
  • Page 22 SLG46140 5.7.2 2 MHz RC Oscillator Table 5. 2 MHz RC OSC frequency limits Temperature Range Power Supply Range +25 °C 0 °C ... +85 °C -40 °C ... +85 °C (VDD) V Minimum Maximum Minimum Maximum Minimum Maximum Value, MHz Value, MHz Value, MHz Value, MHz...
  • Page 23 SLG46140 5.7.3 25 MHz Ring Oscillator Table 7. 25 MHz Ring OSC Frequency Limits Temperature Range Power Supply Range +25 °C 0 °C ... +85 °C -40 °C ... +85 °C (VDD) V Minimum Maximum Minimum Maximum Minimum Maximum Value, MHz Value, MHz Value, MHz Value, MHz...
  • Page 24 SLG46140 5.7.4 1.9 kHz LF Oscillator Table 9. 1.9 kHz LF OSC Frequency Limits Temperature Range Power Supply Range +25 °C 0 °C ... +85 °C -40 °C ... +85 °C (VDD) V Minimum Maximum Minimum Maximum Minimum Maximum Value, kHz Value, kHz Value, kHz Value, kHz...
  • Page 25 SLG46140 5.8 ACMP Specifications Table 12. ACMP Specifications Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit Positive Input VDD = 1.8 V ± 5 % Negative Input Positive Input ACMP Input Voltage VDD = 3.3 V ± 10 % ACMP Range Negative Input Positive Input...
  • Page 26 SLG46140 Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit LB - Enabled, 28.6 = 25 mV T = 25°C = Vin - V LB - Disabled, = Vin + V 13.8 33.2 T = 25°C LB - Enabled, 43.5 58.5 = 50 mV T = 25°C = Vin - V...
  • Page 27 SLG46140 Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit G = 1, VDD = 1.71 V Vref = 50…1200 mV G = 1, VDD = 3.3 V Vref = 50…1200 mV G = 1, VDD = 5.5 V Vref = 50…1200 mV G = 0.5, VDD = 1.71 V Vref = 50…1200 mV -1.09% 0.55%...
  • Page 28 SLG46140 5.9 ADC Specifications (Including PGA) Note: PGA input voltage should not exceed values given in Section 5.1 Absolute Maximum Conditions. Table 13. Single-Ended ADC Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, unless otherwise specified Symbol Parameter Description/Note Conditions...
  • Page 29 SLG46140 Table 13. Single-Ended ADC Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, unless otherwise specified Symbol Parameter Description/Note Conditions Min. Max. Unit T = 25°C, VDD = 5V ±10% ±2.1 G = 0.25 VDD = 5V ±10% ±3.2 T = 25°C, VDD = 2.5 to 5.5 V ±1.9...
  • Page 30 SLG46140 Table 14. Differential ADC Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, Vcm = 500 mV, unless otherwise specified Symbol Parameter Description/Note Conditions Min. Max. Unit G = 1 -500 G = 2 -250 Input Voltage Range (bit 0 to bit 255), G = 4 -125...
  • Page 31 SLG46140 Symbol Parameter Description/Note Conditions Min. Max. Unit Differential ±0.5 Non-Linearity G = 1, 2, 4, 8, 16 NOISE ±0.5 Note 1: V range is given for stable CMRR > 34 dB. Note 2: To ensure linear operation, absolute input voltage on each pin should not exceed VDD-0.5. 000-0046140-111 Page 30 of 169...
  • Page 32 SLG46140 Table 15. Pseudo-Differential ADC Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, Vcm = 500 mV, unless otherwise specified Symbol Parameter Description/Note Conditions Min. Max. Unit G = 1 Input Voltage Range (bit 0 to bit 255), G = 2 Differential G = 4...
  • Page 33 SLG46140 5.10 PGA Specifications Note: PGA input voltage should not exceed values given in Section 5.1 Absolute Maximum Conditions. Table 16. Single-Ended PGA Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, unless otherwise specified Symbol Parameter Description/Note Conditions Min.
  • Page 34 SLG46140 Table 17. Differential PGA Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, Vcm = 500 mV, unless otherwise specified Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit Offset Voltage (RTO, All gains see Note 1) G = 1 T = 25°C ±1.4 ±5.4...
  • Page 35 SLG46140 Table 18. Pseudo-Differential PGA operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, Vinn = 500 mV, unless otherwise specified Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit Offset Voltage (RTO, All gains see Note 1) T = 25°C, G = 1 ±1.2 ±3.6...
  • Page 36 SLG46140 Table 19. Differential or Pseudo-Differential PGA Operation, ADC - Power Down, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, Vcm = 500 mV, unless otherwise specified Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit Offset Voltage (RTI, All gains T = 25°C, ±1.9...

  • Page 37: Digital-To-Analog Converter

    SLG46140 6.0 Summary of Macrocell Function 6.1 I/O Pins • Digital Input (low voltage or normal voltage, with or without Schmitt Trigger) • Open Drain Outputs (x1, x2, x4) • Push Pull Outputs (x1, x2, x4) • Analog I/O • 10 k/100 k/1 Mpull-up/pull-down resistors •...

  • Page 38: Ring Oscillator

    SLG46140 6.9 Digital Comparators or PWM (3 total) • Three 8-bit 100 kHz PWMs or 10 MHz Digital Comparators Delays/Counters (2 total) • One 14-bit Delay/Counter: Range 1 – 16383 clock cycles • One 8-bit Delay/Counter: Range 1 – 255 clock cycles •...
  • Page 39 SLG46140 7.0 I/O Pins The SLG46140 has a total of 12 general purpose I/O pins (GPIO) which can be configured as either Input or Output, some with special functions (such as outputting the Vref), or serving as a signal for programming of the on-chip NVM. Normal Mode pin definitions are as follows: •...
  • Page 40 SLG46140 7.3 Pull Up/Down Resistors All GPIO pins can be configured with pull up/pull down resistors with selectable values or left floating (no resistor): • Floating • 10 kΩ • 100 kΩ • 1 MΩ The GPI pin (PIN2) can only be configured with pull down resistors with the same values. 7.4 I/O Register Settings 7.4.1 PIN 2 Register Settings Table 20.
  • Page 41 SLG46140 7.4.3 PIN 4 Register Settings Table 22. PIN 4 Register Settings Register Bit Signal Function Register Definition Address PIN 4 Input Mode reg <774:773> 00: Digital Input without Schmitt trigger Control 01: Digital Input with Schmitt trigger 10: Low Voltage Digital Input 11: Analog Input PIN 4 Output Mode reg <776:775>...
  • Page 42 SLG46140 7.4.5 PIN 6 Register Settings Table 24. PIN 6 Register Settings Register Bit Signal Function Register Definition Address PIN 6 Input Mode reg <790:788> 000: Digital in without Schmitt Trigger Control 001: Digital in with Schmitt Trigger 010: Low Voltage Digital In 011: Analog IO 100: Push-Pull Mode 101: NMOS Open-Drain...
  • Page 43 SLG46140 7.4.7 PIN 9 Register Settings Table 26. PIN 9 Register Settings Register Bit Signal Function Register Definition Address PIN 9 Input Mode reg <803:802> 00: Digital Input without Schmitt trigger Control 01: Digital Input with Schmitt trigger 10: Low Voltage Digital Input 11: Analog Input PIN 9 Output Mode reg <805:804>...
  • Page 44 SLG46140 7.4.9 PIN 11 Register Settings Table 28. PIN 11 Register Settings Register Bit Signal Function Register Definition Address PIN 11 Input Mode reg <822:820> 000: Digital in without Schmitt Trigger Control 001: Digital in with Schmitt Trigger 010: Low Voltage Digital In 011: Analog IO 100: Push-Pull Mode 101: NMOS Open-Drain...
  • Page 45 SLG46140 7.4.11 PIN 13 Register Settings Table 30. PIN 13 Register Settings Register Bit Signal Function Register Definition Address PIN 13 Input Mode reg <835:834> 00: Digital Input without Schmitt trigger Control 01: Digital Input with Schmitt trigger 10: Low Voltage Digital Input 11: Analog Input PIN 13 Output Mode reg <837:836>...
  • Page 46 SLG46140 7.5 GPI Structure (for Pin 2) 10 k 90 k pull_up_en 900 k Res_sel[1:0] 00: floating 01: 10 k 10: 100 k 11: 1 M wo_smt_en Non-Schmitt Trigger Input Input Mode [1:0] wi_smt_en Schmitt Trigger 00: Digital In without Schmitt Trigger, wosmt_en=1 Input Digital In 01: Digital In with Schmitt Trigger, smt_en=1...
  • Page 47 SLG46140 7.6 Matrix OE IO Structure 7.6.1 Matrix OE IO Structure (for Pins 3, 4, 5, 7, 12, 13, 14) Input Mode [1:0] 00: Digital In without Schmitt Trigger, wosmt_en=1 wosmt_en Non-Schmitt 01: Digital In with Schmitt Trigger, smt_en=1 Trigger Input 10: Low Voltage Digital In mode, lv_en = 1 11: Analog IO mode Output Mode [1:0]...
  • Page 48 SLG46140 7.6.2 Matrix OE 4x Drive Structure (for Pin 9) The Matrix OE 4x Drive Structure consists of two Matrix OE IO structures (see above section) Mode [1:0] Input Mode [1:0] Mode [3:2] Output Mode [1:0] Pull up Enable Pull up Enable Matrix OE GPIO PAD Res_Sel[1:0 Res_Sel[1:0...
  • Page 49 SLG46140 7.7 Register OE IO Structure 7.7.1 Register OE IO Structure (for Pins 6, 11) Mode [2:0] 000: Digital In without Schmitt Trigger, wosmt_en=1, OE = 0 wosmt_en Non-Schmitt 001: Digital In with Schmitt Trigger, smt_en=1, OE = 0 Trigger Input 010: Low Voltage Digital In mode, lv_en = 1, OE = 0 011: analog IO mode 100: push-pull mode, pp_en=1, OE = 1...
  • Page 50 SLG46140 7.7.2 Register OE 4x Drive Structure (for Pin 10) The Register OE 4x Drive Structure consists of two Register OE IO structures (see above section) Mode [2:0] Mode [2:0] Mode [3:2] 2x_en Pull up Enable Register OE GPIO PAD Pull up Enable Res_Sel[1:0 Res_Sel[1:0...
  • Page 51 SLG46140 8.0 Connection Matrix The Connection Matrix in the SLG46140 is used to create the internal routing for internal functions of the device once it is programmed. The registers are programmed from the one-time NVM cell during Test Mode Operation. All of the connection points for each logic cell within the SLG46140 have a specific digital bit code assigned to it that is either set to active “High”...
  • Page 52 SLG46140 8.1 Matrix Input Table Table 32. Matrix Input Table Matrix Decode Matrix Input Signal Function GROUND LUT2_0 output LUT2_1 output LUT2_2 output LUT2_3 output LUT2_4 / DFF0/Latch0 output LUT2_5 / DFF1/Latch1 output LUT3_0 output LUT3_1 output LUT3_2 output LUT3_3 output LUT3_4 / DFF2/Latch2 output LUT3_5 / DFF3/Latch3 output LUT4_0 output/PGEN output...
  • Page 53 SLG46140 Table 32. Matrix Input Table Matrix Decode Matrix Input Signal Function CNT1/DLY1 output CNT2/DLY2 / LUT4_1 output CNT3/DLY3 / LUT3_7 output PWM0_DCMP0_Out_positive PWM0_DCMP0_Out_negative PWM1_DCMP1_Out_positive PWM1_DCMP1_Out_negative PWM2_DCMP2_Out_positive PWM2_DCMP2_Out_negative SPI interrupt ACMP0 output ACMP1 output ADC interrupt bg_ok signal (delay 200ns) power detector output no divider RC oscillator output GROUND...
  • Page 54 SLG46140 Matrix Output Table Table 33. Matrix Output Table Register Bit Matrix Output Matrix Output Signal Function Address Number reg<5:0> In0 of LUT2_0 reg<11:6> In1 of LUT2_0 reg<17:12> In0 of LUT2_1 reg<23:18> In1 of LUT2_1 reg<29:24> In0 of LUT2_2 reg<35:30> In1 of LUT2_2 reg<41:36>...
  • Page 55 SLG46140 Table 33. Matrix Output Table Register Bit Matrix Output Matrix Output Signal Function Address Number reg<233:228> Data of DFF/Latch 5 reg<239:234> Clock of DFF/Latch 5 reg<245:240> Clock of Pipe Delay / In0 of LUT3_6 reg<251:246> In of Pipe Delay / In1 of LUT3_6 reg<257:252>...
  • Page 56 SLG46140 Table 33. Matrix Output Table Register Bit Matrix Output Matrix Output Signal Function Address Number reg<449:444> Keep of DLY/CNT3 (FSM1) In1 of LUT3_7 Up of DLY/CNT3 (FSM1) reg<455:450> In2 of LUT3_7 reg<461:456> PWM/DCMP0 Positive Input and PWM/DCMP1 Negative Input Register Selection Bit 0 reg<467:462>...
  • Page 57 SLG46140 9.0 8-bit SAR ADC Analog-to-Digital Converter (ADC) The Analog to Digital Converter in the SLG46140 is an 8-bit Successive Approximation Register Analog to Digital Converter (SAR ADC) which operates at a sampling speed of 100 kHz. The ADC’s DNL < ± 0.5 LSB and INL < ± 3.4 LSB and has a ADC V accuracy of ±...
  • Page 58 SLG46140 9.1 ADC Functional Diagram PGAOUT_en reg <559> PGA OUT CH Select (PIN 11) ADC Programmable Gain Amplifier to ACMP reg <530> Pin 7 SER DATA Gain Sel reg <534:532> Pin 6 PAR DATA PGA Power reg <535> INT OUT ADC V Reserved DAC_in_en reg <529>...
  • Page 59 SLG46140 9.2 ADC Operation Modes The ADC has three operating modes: • Single-Ended ADC operation using IN+ from PIN 6 or 7, when ADC_sel (reg <531>) is “0” • Differential ADC operation using IN+ from PIN 6 and IN- from PIN 7, when ADC_sel (reg <531>) is “1” •...
  • Page 60 SLG46140 9.3.2 PGA Output PGA can be used either in standalone mode or as ADC font-end / ACMP input buffer. In PGA standalone mode (ADC in POWER DOWN mode) PGA output is always referenced to GND. When ADC is powered on, it powers also the PGA output reference macrocell, so that the output voltage is referenced to one of predefined output offset voltages Vos(RTO) which can be found in PGA specifications.
  • Page 61 SLG46140 Table 34. PGA Register Settings Register Bit Signal Function Register Definition Address Multichannel Input MUX 0: Disable (PIN11 can not control) <530> Enable (Controlled By Pin11) 1: Enable 0: Single ended PGA Input Mode Control <531> 1: Differential input 000: 0.25x (For single-ended operation only) 001: 0.5x (For single-ended operation only) 010: 1x...
  • Page 62 SLG46140 9.3.5 PGA Typical Performance 200 samples 200 samples VDD = 5.0 V = 3.3 V T = 25°C T = 25°C Vos, mV Vos, mV Figure 12. PGA Input Offset Distribution, Single-Ended Figure 11. PGA Input Offset Distribution, Single-Ended Mode, G = 0.25 Mode, G = 0.5 200 samples...
  • Page 63 SLG46140 200 samples 200 samples = 3.3 V = 3.3 V T = 25°C T = 25°C Vos, mV Vos, mV Figure 15. PGA Input Offset Distribution, Single-Ended Figure 16. PGA Input Offset Distribution, Single-Ended Mode, G = 4 Mode, G = 8 1000 1200 1000...
  • Page 64 SLG46140 -0.5 -0.5 -1.5 -1.5 -2.5 -2.5 -40°C -3.5 -3.5 -40°C +25°C +25°C +85°C +85°C -4.5 -4.5 Figure 19. Typical PGA Gain Error vs. Vin, Single-Ended Figure 20. Typical PGA Gain Error vs. Vin, Single-Ended Mode, G = 8, VDD = 1.71 V Mode, G = 8, VDD = 5.5 V -600 -400...
  • Page 65 SLG46140 -600 -400 -200 -0.2 -0.5 -0.4 -40°C -0.6 +25°C -0.8 +85°C -1.5 -1.2 -40°C -1.4 +25°C -1.6 -2.5 +85°C -1.8 Figure 23. Typical PGA Gain Error vs. Vin, Differential Figure 24. Typical PGA Gain Error vs. Vin, Differential Mode, G = 1, VDD = 5.5 V Mode, G = 16, VDD = 1.71 V 1200 1000...
  • Page 66 SLG46140 1200 1200 1000 1000 Vdd ≥ 3.3V Vdd ≥ 3.3V Vdd = 1.71V Vdd = 1.71 1000 1200 1400 1600 1000 1200 1400 1600 Vinn, mV Vinn, mV Figure 27. PGA Input Vind Range Multiplied by Gain vs. Figure 28. PGA Input Vind Range Multiplied by Gain vs. Vinn, Pseudo-Differential Mode, G = 2 Vinn, Pseudo-Differential Mode, G = 4 1000...
  • Page 67 SLG46140 -0.5 -0.5 -1.5 -1.5 -40°C -40°C +25°C +25°C -2.5 -2.5 +85°C +85°C Figure 31. Typical PGA Gain Error vs. Vin, Figure 32. Typical PGA Gain Error vs. Vin, Pseudo-Differential Mode, G= 4, VDD = 1.71 V Pseudo-Differential Mode, G= 4, VDD = 5.5 V 9.4 ADC Input Voltage Definition The ADC’s input voltage (V ) is calculated based on either the single-ended or differential operation modes the logic cell is...
  • Page 68 SLG46140 and V - absolute voltage at negative and positive PGA input correspondingly - common mode PGA voltage: ---------------------------- Note: In Pseudo-Differential mode V is replaced by V voltage for convenience ADC code for PGA differential input voltage V can be calculated as follows: •...
  • Page 69 SLG46140 9.5 ADC Reference Voltage The ADC’s reference voltage (V ) is controlled by ADC_Vref_sel (reg <546:545>). The two reference inputs are chosen from the following: • ADC V from Internal Source (ADC V = 1.2 V) • Power Divider of (0.25) * V ADC V Reserved * (0.25)
  • Page 70 SLG46140 reg <578> Ring Osc Matrix Out <67> RC Osc SPI CLK ADC CLK SRC reg <580:579> Figure 34. ADC Clock Source 9.8 ADC Outputs The ADC’s output can be shifted out through the SPI logic cell. Both SER DATA and PAR DATA produce an 8-bit data string over 16 clock cycles.
  • Page 71 SLG46140 9.9 ADC Interrupt Output Timing Diagram Power_Down T_ADC_startup > 500s (force analog disable) T_ADC_startup > 5 s (force analog enable) CLK case 1 CLK case 2 SER DATA SER DATA PAR DATA PAR DATA ADC_int First pulse Bandgap OK Figure 35.
  • Page 72 SLG46140 9.10 ADC Register Settings Table 35. ADC Register Settings Register Bit Signal Function Register Definition Address 00: Reserved 01: Reserved ADC Speed Selection <543:542> 10: 100 kHz 11: Reserved 00: ADC V 01: Reserved ADC Vref Source Select <546:545> 10: 1/4 Vdd 11: None 0: Disable...

  • Page 73: 8-Bit Digital-To-Analog Converter (Dac)

    SLG46140 10.0 8-bit Digital-to-Analog Converter (DAC) There are two DACs in the SLG46140 (DAC0 and DAC1), they are 8-bit Digital to Analog Converters which operate at a maximum sampling speed of 100 ksps. The DAC's DNL is less than 1LSB and INL is less than 1LSB. DAC output to PIN resistance is 1 k. Load resistance is recommended to be no less than 10 k;...
  • Page 74 SLG46140 10.1 DAC0 Functional Diagram reg <547> Pin3_aio_en reg <767:766>=11 Register Vref Out_1 (Pin3) DAC0 DCMP1's neg. input PWR DOWN reg <528:527> reg <544> PGA negative input ACMP0 negative input ACMP1 negative input Figure 36. DAC0 Functional Diagram 10.2 DAC1 Functional Diagram reg <556>...
  • Page 75 SLG46140 10.3 DAC Register Settings Table 36. DAC Register Settings Register Bit Signal Function Register Definition Address ADC native input from internal 0: disable reg<529> DAC0 1: enable 0: power down reg<538> DAC1 power on signal 1: power on 0: power down reg<544>...
  • Page 76 SLG46140 11.0 Combinatorial Logic Combinatorial logic is supported via nine Lookup Tables (LUTs) within the SLG46140. There are four 2-bit LUTs and four 3-bit LUTs. The device also includes eight Combination Function Macrocells that can be used as LUTs. For more details, please see Section 12.0 Combination Function Macrocells.
  • Page 77 SLG46140 Table 41. 2-bit LUT Standard Digital Functions Function AND-2 NAND-2 OR-2 NOR-2 XOR-2 XNOR-2 11.2 3-Bit LUT The seven 3-bit LUTs each take in three input signals from the connection matrix and produce a single output, which goes back into the connection matrix.
  • Page 78 SLG46140 Table 42. 3-bit LUT0 Truth Table Table 44. 3-bit LUT2 Truth Table reg <874> reg <890> reg <875> reg <891> reg <876> reg <892> reg <877> reg <893> reg <878> reg <894> reg <879> reg <895> reg <880> reg <896> reg <881>...
  • Page 79 SLG46140 12.0 Combination Function Macrocells The SLG46140 has eight combination function macrocells that can serve more than one logic or timing function. In each case, they can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be implemented in these macrocells: •...
  • Page 80 SLG46140 From Connection Matrix Output <9> 2-bit LUT4 To Connection Matrix reg <866> Input <5> 4-bits NVM Init. Polarity Select reg <867:864> DFF0 From Connection Matrix Output <8> Q/nQ reg <864> Latch Mode Select reg <865> Output Select (Q or nQ) 1-bit NVM reg <868>...
  • Page 81 SLG46140 12.1.1 2-Bit LUT or D Flip Flop Macrocells Used as 2-Bit LUTs Table 47. 2-bit LUT4 Truth Table. Table 48. 2-bit LUT5 Truth Table. reg <864> reg <869> reg <865> reg <870> reg <866> reg <871> reg <867> reg <872> 12.1.2 2-Bit LUT or D Flip Flop Macrocells Used as D Flip Flop Register Settings Table 49.
  • Page 82 SLG46140 12.2 3-Bit LUT or D Flip Flop with Set/Reset Macrocells There are two macrocells that can serve as either 3-bit LUTs or as D Flip Flops. When used to implement LUT functions, the 3-bit LUTs each take in three input signals from the connection matrix and produce a single output, which goes back into the connection matrix.

  • Page 83: Register Definition

    SLG46140 12.2.1 3-Bit LUT or D Flip Flop Macrocells Used as 3-Bit LUTs Table 51. 3-bit LUT4 Truth Table Table 52. 3-bit LUT4 Truth Table reg <906> reg <916> reg <907> reg <917> reg <908> reg <918> reg <909> reg <919> reg <910>...
  • Page 84 SLG46140 12.3 3-Bit LUT or Pipe Delay Macrocell There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay. When used to implement LUT functions, the 3-bit LUT take in three input signals from the connection matrix and produces a single output, which goes back into the connection matrix.

  • Page 85: Signal Function

    SLG46140 12.3.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT Table 55. 3-bit LUT6 Truth Table reg <750> reg <751> reg <752> reg <753> reg <754> reg <755> reg <756> reg <757> Each Macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function: 3-Bit LUT6 is defined by reg<757:750>...
  • Page 86 SLG46140 12.4 3-bit LUT or 8-Bit Counter / Delay Macrocells There is one macrocell that can serve as either a 3-bit LUT or as a Counter / Delay. When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection matrix and produces a single output, which goes back into the connec- tion matrix.
  • Page 87 SLG46140 12.4.1 3-Bit LUT or 8-Bit Counter / Delay Macrocells Used as 3-Bit LUT Table 57. 3-bit LUT6 Truth Table reg <661> reg <662> reg <663> reg <664> reg <665> reg <666> reg <667> reg <668> Each Macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function: 3-Bit LUT7 is defined by reg<668:661>...
  • Page 88 SLG46140 Table 58. CNT/DLY2 Register Settings Register Bit Signal Function Address Register Definition FSM Input Data reg <679:678> 00: 8 bits counter data Source Select 01: 8bits ADC data 10: no Data 11: 8MSBs SPI parallel data 000-0046140-111 Page 87 of 169...
  • Page 89 SLG46140 12.5 4-bit LUT or Programmable Pattern Generator (PGEN) The SLG46140 has one combination function macrocell that can serve as a logic or timing function. This macrocell can serve as a Look Up Table (LUT), or Programmable Pattern Generator (PGEN). When used to implement LUT functions, the 4-bit LUT takes in four input signals from the connection matrix 0 and produce a single output, which goes back into the connection matrix 0.
  • Page 90 SLG46140 nRST 12 13 Figure 47. PGEN Timing Diagram 000-0046140-111 Page 89 of 169...
  • Page 91 SLG46140 When this macrocell is used to implement LUT function, the 4-bit LUT uses a 16-bit register signal to define its output function; 4-Bit LUT0 is defined by reg<945:930>. Table 59. 4-bit LUT0 Truth Table reg <930> reg <931> reg <932> reg <933>...
  • Page 92 SLG46140 12.6 4-Bit LUT or 14-Bit Counter / Delay Macrocells There is one macrocell that can serve as a 4-bit LUT or as Counter / Delay. When used to implement LUT functions, the 4-bit LUTs each take in four input signals from the connection matrix and produce a single output, which goes back into the connection matrix.
  • Page 93 SLG46140 12.6.1 4-Bit LUT or 14-Bit Counter / Delay Macrocell Used as 4-Bit LUT Table 62. 4-bit LUT1 Truth Table reg <680> reg <681> reg <682> reg <683> reg <684> reg <685> reg <686> reg <687> reg <688> reg <689> reg <690>...
  • Page 94 SLG46140 12.6.2 4-Bit LUT or as 14-Bit Counter / Delay Register Settings Table 64. CNT/DLY2 Register Settings Register Bit Signal Function Address Register Definition LUT4_1 data [bits reg<693:680> data 13:0] (if reg<702:701>=11) DLY2/CNT2/FSM0 data reg<694> 0: reset to 0s LUT4_1 data [bit 14] 1: set to Data.
  • Page 95 SLG46140 13.0 Analog Comparators (ACMP) There are two Analog Comparator (ACMP) macrocells in the SLG46140. In order for the ACMP cells to be used in a GreenPAK design, the power up signals (ACMPx_pdb) need to be active. By connecting to signals coming from the Connection Matrix, it is possible to have each ACMP be on always on, always off, or power cycled based on a digital signal coming from the Connection Matrix.
  • Page 96 SLG46140 Table 66. Gain Divider Accuracy Gain x0.5 x0.33 x0.25 Accuracy -0.83% -0.83% -0.78% +0.73% +0.96% +1.14% Each cell also has a hysteresis selection, to offer hysteresis of 0 mV, 25 mV, 50 mV or 200 mV. The 50 mV and 200 mV hysteresis options can be used with internal voltage reference only.
  • Page 97 SLG46140 13.1 ACMP0 Block Diagram reg <524> reg <511:510> reg <526:525> Selection Hysteresis Selection reg <523:522> PIN 10 PGA_OUT Selectable To Connection Gain Matrix Input<48> Vref DAC0_OUT 11111 DAC1_OUT 11110 PIN4/2 11101 PIN5/2 11100 PIN4 11011 PIN5 11010 VDD/4 11001 VDD/3 11000 From Connection...
  • Page 98 SLG46140 13.2 ACMP0 Register Settings Table 68. ACMP0 Register Settings Register Bit Signal Function Address Register Definition ACMP0 In Voltage reg<500:496> 00000: 50 mV 00001: 100 mV Select 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV...
  • Page 99 SLG46140 13.3 ACMP1 Block Diagram reg <518> reg <509:508> reg <517:516> Selection Hysteresis Selection reg <520:519> PIN 9 PGA_OUT Selectable To Connection Gain Matrix Input<49> PIN 10 Vref DAC0_OUT 11111 DAC1_OUT 11110 PIN4/2 11101 PIN5/2 11100 PIN4 11011 PIN5 11010 VDD/4 11001 VDD/3...
  • Page 100 SLG46140 13.4 ACMP1 Register Settings Table 69. ACMP1 Register Settings Register Bit Signal Function Address Register Definition ACMP1 In Voltage reg<505:501> 00000: 50 mV 00001: 100 mV Select 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV...
  • Page 101 SLG46140 14.0 Digital Storage Elements (DFFs/Latches) There are six Combination Function macrocells that can be used to implement D-Flip Flop or Latch functions. Please see Section 12.1 2-Bit LUT or D Flip Flop Macrocells and Section 12.2 3-Bit LUT or D Flip Flop with Set/Reset Macrocells for the description of this Combination Function macrocell.
  • Page 102 SLG46140 14.1 Initial Polarity Operations Figure 54. DFF Polarity Operations 000-0046140-111 Page 101 of 169...
  • Page 103 SLG46140 Figure 55. DFF Polarity Operations with nReset 000-0046140-111 Page 102 of 169...
  • Page 104 SLG46140 Figure 56. DFF Polarity Operations with nSet 000-0046140-111 Page 103 of 169...
  • Page 105 SLG46140 15.0 Counters/Delay Generators (CNT/DLY) There are two configurable counters/delay generators in the SLG46140. One of the counter/delay generators (CNT/DLY 0) is 14-bit, and the other counter/delay generator (CNT/DLY 1) is 8-bit. For flexibility, each of these macrocells has a large selection of internal and external clock sources, as well as the option to chain from the output of the previous (N-1) CNT/DLY macrocell, to implement longer count / delay circuits.
  • Page 106 SLG46140 Mode Select: reg <719:718> From Connection Matrix Output <69> Edge Detector reg <721:720> reg <717:714> Delay_out To Connection Matrix Input <38> CK_RCOSC CK_RCOSC/4 CK_RCOSC/12 CK_RCOSC/24 CK_RCOSC/64 CNT_END0 CNT/DLY1 Matrix0_out67 Counter_end Matrix0_out67 div 8 CK_RINGOSC Matrix0_out80 (SPI_SCLK) CK_LFOSC CKFSM_DIV256 CKPWM Reserved Reserved Counter Control Data...
  • Page 107 SLG46140 15.1 CNT/DLY Timing Diagrams 15.1.1 Delay Mode (counter data: 3) CNT/DLY0...CNT/DLY9 DLYIN offset period CLK (OSC force on) DLYOUT delay = offset + period x (count_data + 1) offset = (0 or 1) * period DLYIN offset CLK (single DLY usage, OSC is autopower on) DLYOUT delay = offset + period x (count_data + 1)
  • Page 108 SLG46140 15.1.2 Counter Mode (counter data: 3) CNT/DLY0...CNT/DLY9 RESETIN The pulse width is about 10 ns, depending on PVT EDGE DETECT OUT 4 clk period pulse Note: Q = current counter value Figure 61. Timing (reset rising edge mode, oscillator is forced on) for count data = 3 RESETIN FROM MATRIX The pulse width is about 10 ns, depending on PVT...
  • Page 109 SLG46140 15.1.3 CNT/FSM Mode CNT/DLY2, CNT/DLY4 RESETIN KEEP COUNT_END Note: Q = current counter value Figure 64. CNT/FSM Timing Diagram (reset rising edge mode, oscillator is forced on, UP=0) for counter data = 3 RESETIN KEEP COUNTEND Note: Q = current counter value Figure 65.
  • Page 110 SLG46140 RESETIN KEEP COUNTEND 253 254 255 FSM0 16383 Note: Q = current counter value FSM1 255 Figure 66. CNT/FSM Timing Diagram (reset rising edge mode, oscillator is forced on, UP=1) for counter data = 3 RESETIN KEEP COUNTEND 253 254 255 FSM0 16383 Note: Q = current counter value FSM1 255...
  • Page 111 SLG46140 15.2 CNT/DLY0 Register Settings Table 70. CNT/DLY0 Register Settings Register Bit Signal Function Address Register Definition Counter0 Control reg<735:722> 1-16384: (delay time = (counter control data +2) /freq) Data/Delay0 Time Control Counter/Delay0 reg<740:737> 0000: CK_RCOSC Clock Source Select 0001: CK_RCOSC_DIV4 0010: CK_RCOSC_DIV12 0011: CK_RCOSC_DIV24 0100: CK_RCOSC_DIV64...
  • Page 112 SLG46140 15.3 CNT/DLY1 Register Settings Table 71. CNT/DLY1 Register Settings Register Bit Signal Function Address Register Definition Counter1 Control reg<712:705> 1-255: (delay time = (counter control data +2) /freq) Data/Delay1 Time Control Counter/Delay1 reg<717:714> 0000: CK_RCOSC Clock Source select 0001: CK_RCOSC_DIV4 0010: CK_RCOSC_DIV12 0011: CK_RCOSC_DIV24 0100: CK_RCOSC_DIV64...
  • Page 113 SLG46140 15.4 CNT/DLY2 Register Settings Table 72. CNT/DLY2 Register Settings Register Bit Signal Function Address Register Definition Counter2 Control reg<693:680> 1-16384: (delay time = (counter control data +2) /freq) Data/Delay2 Time Control Counter/Delay2 reg<698:695> 0000: CK_RCOSC Clock Source Select 0001: CK_RCOSC_DIV4 0010: CK_RCOSC_DIV12 0011: CK_RCOSC_DIV24 0100: CK_RCOSC_DIV64...
  • Page 114 SLG46140 15.5 CNT/DLY3 Register Settings Table 73. CNT/DLY3 Register Settings Register Bit Signal Function Address Register Definition Counter3 Control reg<668:661> 1-255: (delay time = (counter control data +2) /freq) Data/Delay3 Time Control Counter/Delay3 reg<673:670> 0000: CK_RCOSC Clock Source Select 0001: CK_RCOSC_DIV4 0010: CK_RCOSC_DIV12 0011: CK_RCOSC_DIV24 0100: CK_RCOSC_DIV64...
  • Page 115 SLG46140 16.0 Digital Comparator (DCMP) / Pulse Width Modulator (PWM) The SLG46140 has three 8-bit digital comparator / pulse width modulator logic cells. Each of these three logic cells can be either a digital comparator (DCMP) or a pulse width modulator (PWM) independently of how the other two logic cells are defined. Both the DCMP and PWM logic can operate at up to a frequency of 10MHz.
  • Page 116 SLG46140 • 8-bit signal from the SPI logic cell output (SPI<15:8> for DCMP0 and DCMP1 or SPI<7:0> for DCMP2) • 8-bit signal from the FSM0<7:0> • 8-bit user defined signal value IN-’s 8-bit data string for all PWMs is sourced from an 8-bit signal from CNT/DLY. 000-0046140-111 Page 115 of 169...
  • Page 117 SLG46140 16.4 PWM Output Modes The output (OUT+) duty cycle can be set to either count down to 0% or count up to 100% and each PWM is independently controlled by the value of reg<614> (PWM0), reg<603> (PWM1), and reg<592> (PWM2). When both inputs are equal the output signal (EQ) will go high.
  • Page 118 SLG46140 16.6 DCMP1/PWM1 Functional Diagram reg <653> Connection Matrix Output <78> PWM PD reg <601> Select reg <607:606> ADC<7:0> 8 LSBs SPI Connection Matrix Output <77:76> FSM1<7:0> reg1 DCMP1/PWM1 To Connection Matrix Input <43> reg <652:645> FSM1<7:0> OUT+ reg <644:637> To Connection Matrix Input <44>...
  • Page 119 SLG46140 16.8 PWM Dead Band Control The dead band interval can be controlled with NVM bits from PWM0 reg<616:615>, from PWM1 reg<605:604>, from PWM2 reg<594:593>. The typical dead band time starts at 8 ns and can go to 64 ns, increasing by 8 ns intervals. For the Delay dead band control, the dead time control range is: = (PWM Register bits + 1) x 8ns 16.9 PWM Dead Band Control Timing Diagram...

  • Page 120: Signal Function

    SLG46140 16.12 DCMP/PWM Register Settings Table 74. DCMP/PWM Register Settings Register Bit Signal Name Signal Function Register Definition Address PWMDCMP2_pd PWM2/DCMP2 power 0: power down <590> down control 1: power on PWMDCMP2_clk_in PWM/DCMP2 clock 0: Disable <591> invert 1: Enable PWM2_mode_sel PWM2 mode select 0: count down to 0%...

  • Page 121: Signal Name

    SLG46140 Table 74. DCMP/PWM Register Settings Register Bit Signal Name Signal Function Register Definition Address PWMDCMP0_pos_in PWM0/DCMP0 positive 00: ADC [7:0] input source select 01: 8MSBs SPI <618:617> 10: FSM0[7:0] 11: regs from MUX controlled by matrix_out[77:76] PWMDCMP0_neg_in PWM0/DCMP0 negative 00: FSM0[7:0] input source select 01: reg0...
  • Page 122 SLG46140 17.0 Slave SPI - Serial to Parallel / Parallel to Serial Converter (SPI) The Slave SPI data can be communicated between the SLG46140 and the larger system design through either the serial to parallel or parallel to serial interface. The SPI has two 8-bit registers (2 bytes) that are used for data transfer. The external clock signal and the nCSB (Enable Control Signal) comes from the Connection Matrix Out.
  • Page 123 SLG46140 17.2 Clock polarity and phase In addition to setting the clock frequency, it is possible to configure the clock polarity and phase with respect to the data. This is configured by the CPOL and CPHA bits respectively. Figure 73 shows the SPI timing diagram when CPHA = 0; in this mode data can only be transmitted from serial to parallel, not from parallel to serial.
  • Page 124 SLG46140 SCLK (CPOL=0) SCLK (CPOL=1) Bit[1] Bit[1] Interrupt Bit[1] Bit[1] Figure 74. Timing Diagram showing Clock Polarity and Phase, CPHA = 1 Table 76. CPHA = 1 Timing Characteristics Parameter Symbol Units SCLK period SCLK pulse width high SCLK pulse width low CSB fall to SCLK first edge setup SCLK last edge to CSB rise hold SCLK to SDO hold...
  • Page 125 SLG46140 • At CPOL=0 the base value of the clock is zero • For CPHA=0, data are captured on the clock's rising edge (LOW→HIGH transition) and data is propagated on a falling edge. (HIGH→LOW clock transition). • For CPHA=1, data are captured on the clock's falling edge and data is propagated on a rising edge. •...
  • Page 126 SLG46140 17.4 SPI data buffer function SPI data buffer can be used to have DCMP compare two different ADC timing data. The ADC buffer is shared with the DFFs that are in the SPI macrocell. When the SPI is set to ADC buffer mode (reg[654]=1), the DFF ‘s data inputs of SPI’s parallel outputs are from ADC (reg[655]=1), and the DFF’s clock source comes from matrix_output80 which can be programmed by user.
  • Page 127 SLG46140 18.0 Pipe Delay (PD) The SLG46140 has one 16-stages DFF Pipe Delay Macrocell. The Pipe Delay has three input signals from the matrix, Input (IN), Clock (CLK) and Reset (RST). The pipe delay cell is built from 16 D Flip-Flop logic cells that provide two delay options which are user selectable. The DFF cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell.

  • Page 128: Programmable Delay

    SLG46140 19.0 Programmable Delay / Edge Detector The SLG46140 has one programmable time delay logic cell available that can generate a delay that is selectable from one of four timings (time1) configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay patterns, rising edge detection, falling edge detection, both edge detection and both edge delay.
  • Page 129 SLG46140 time1 time1 Delayed Rising Edge Detector Delayed Edge Delayed Falling Edge Detector Detector Output Delayed Both Edge Detector Delayed Both Edge Delay time2 time2 time1 can be set by register value (150 ns, 300 ns, 450 ns, 600 ns) time2 is a fixed value at ~200 ns Figure 80.
  • Page 130 SLG46140 19.3 Programmable Delay 0 Register Settings Table 78. Programmable Delay 0Register Settings Register Bit Signal Function Address Register Definition Select the edge reg<487:486> 00: Rising Edge Detector mode of 01: Falling Edge Detector programmable 10: Both Edge Detector delay & edge 11: Both Edge Delay detector Delay value select...

  • Page 131: Voltage Reference (Vref)

    SLG46140 20.0 Voltage Reference (VREF) 20.1 Voltage Reference Overview The SLG46140 has a Voltage Reference Macrocell to provide references to the two analog comparators. This macrocell can supply a user selection of fixed voltage references, /3 and /4 reference off of the V power supply to the device, and externally supplied voltage references from pins 4 and 5.
  • Page 132 SLG46140 Table 80. VREF Range Practical VREF Range Note 2.0 V - 5.5 V 50 mV ~1.2 V Do not use external Vref when VDD > 5.0 V and T = 85°C 1.7 V - 2.0V 50 mV ~1.1 V Do not operate above 1.1 V 20.2 VREF Block Diagram reg <500:496>...
  • Page 133 SLG46140 21.0 Oscillators The SLG46140 has two internal RC oscillators (25 kHz or 2 MHz, user selectable), as well as one Low-Frequency oscillator (1.9 kHz) and one Ring oscillator (25 MHz). There are two divider stages for the RC and Ring oscillators, and one divider stage for the Low-Frequency oscillator, that allow the user flexibility for introducing clock signals to connection matrix, as well as various other Macrocells.
  • Page 134 SLG46140 reg <570> PWR DOWN reg <569:568> Matrix Output <66> reg <573:571> 1/2/4/3/8/12/24/64 divs Matrix Input <35> RC Osc DIV1/2/4/8 (2 MHz, 25kHz) Matrix IN0_50 shared with reg <561:560> wake/sleep oscillator LF Osc DIV1/2/4/16 (1.9 kHz) Matrix Out Matrix Output <67> reg<3:0>...
  • Page 135 SLG46140 21.1 Oscillator Power On delay Power On OSC enable Delay Figure 84. Oscillator Startup Diagram Note 1: OSC power mode: "Auto Power On”. Note 2: ‘OSC enable’ signal appears when any block that uses OSC is powered on. VDD (V) Figure 85.
  • Page 136 SLG46140 1 100 1 050 1 000 VDD (V) Figure 86. RC Oscillator Maximum Power On Delay vs. VDD at room temperature, RC OSC=2 MHz. VDD (V) Figure 87. RC Oscillator Maximum Power On Delay vs. VDD at room temperature, RC OSC=25 kHz. 000-0046140-111 Page 135 of 169...
  • Page 137 SLG46140 VDD (V) Figure 88. Ring Oscillator Maximum Power On Delay vs. VDD at room temperature. 21.2 Oscillator Accuracy Fmax @ VDD=1.8 V Fmin @ VDD=1.8 V Fmax @ VDD=3.3 V Fmin @ VDD=3.3 V Fmax @ VDD=5.0 V Fmin @ VDD=5.0 V T (°C) Figure 89.
  • Page 138 SLG46140 Fmax @ VDD=1.8 V Fmin @ VDD=1.8 V Fmax @ VDD=3.3 V Fmin @ VDD=3.3 V 26.5 Fmax @ VDD=5.0 V Fmin @ VDD=5.0 V 25.5 24.5 23.5 T (°C) Figure 90. RC Oscillator Frequency vs. Temperature, RC OSC=25 kHz Fmax @ VDD=1.8 V Fmin @ VDD=1.8 V Fmax @ VDD=3.3 V...
  • Page 139 SLG46140 Fmax @ VDD=1.8 V Fmin @ VDD=1.8 V Fmax @ VDD=3.3 V Fmin @ VDD=3.3 V Fmax @ VDD=5.0 V Fmin @ VDD=5.0 V T (°C) Figure 92. Ring Oscillator Frequency vs. Temperature, Ring OSC=25 MHz Note: For more information see section 5.7 OSC Specifications. 000-0046140-111 Page 138 of 169...

  • Page 140: Power On Reset (Por)

    SLG46140 22.0 Power On Reset (POR) The SLG46140 has a power-on reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first ramping to the device, and also while the VDD is falling during power-down.
  • Page 141 SLG46140 22.2 POR Sequence The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 93. POR_NVM (reset for NVM) NVM_ready_out POR_GPI (reset for input enable) POR_LUT (reset for LUT output) POR_CORE (reset for DLY/RCO/DFF /Latch/Pipe DLY POR_OUT (generate low to high to matrix)
  • Page 142 SLG46140 22.3 Macrocells Output States During POR Sequence To have a full picture of SLG46140 operation during powering and POR sequence, review the overview the macrocell output states during the POR sequence (Figure 94 describes the output signals states). First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output PINs which are in high impedance state).
  • Page 143 SLG46140 The VREF output pin driving signal can precede POR output signal going high by 3 s - 5 s. The POR signal going high indicates the mentioned powerup sequence is complete. Note: The maximum voltage applied to any PIN should not be higher than the VDD level. There are ESD Diodes between PIN – >...
  • Page 144 SLG46140 Note that during External Reset the output pin's status will depend on the OE control circuits and current consumption is deter- mined by the design. External Reset high active POR_NVM (reset for NVM) NVM_ready_out POR_GPI (reset for input enable) POR_LUT (reset for LUT output) POR_CORE...
  • Page 145 SLG46140 External Reset rising edge detect POR_NVM (reset for NVM) NVM_ready_out POR_GPI (reset for input enable) POR_LUT (reset for LUT output) POR_CORE (reset for DLY/RCO/DFF /Latch/Pipe DLY POR_OUT (generate low to high POR_GPO (reset for output en- Figure 97. External reset sequence (Rising edge detect). 000-0046140-111 Page 144 of 169...
  • Page 146 SLG46140 External Reset falling edge detect POR_NVM (reset for NVM) NVM_ready_out POR_GPI (reset for input enable) POR_LUT (reset for LUT output) POR_CORE reset for DLY/RCO/DFF /Latch/Pipe DLY POR_OUT (generate low to high POR_GPO (reset for output en- Figure 98. External reset sequence (Falling edge detect). Table 82.
  • Page 147 SLG46140 23.0 Appendix A - SLG46140 Register Definition Register Bit Signal Function Register Bit Definition Address reg<5:0> in0 of LUT2_0 (out0) reg<11:6> in1 of LUT2_0 (out1) reg<17:12> in0 of LUT2_1 (out2) reg<23:18> in1 of LUT2_1 (out3) reg<29:24> in0 of LUT2_2 (out4) reg<35:30>...
  • Page 148 SLG46140 Register Bit Signal Function Register Bit Definition Address reg<251:246> in of pipe delay / in1 of LUT3_6 (out41) reg<257:252> porb of pipe delay / in2 of LUT3_6 (out42) reg<263:258> input of edge detector and programmable delay (out43) reg<269:264> digital output of PIN3 (out44) reg<275:270>...
  • Page 149 SLG46140 Register Bit Signal Function Register Bit Definition Address Programmable Delay 00: rising edge detect 01: falling edge detect reg<487:486> Mode selection 10: both edge detect 11: both edge delay 00: 110 ns delay 01: 220 ns delay reg<489:488> Delay time selection 10: 330 ns delay 11: 440 ns delay 0: output no delay...
  • Page 150 SLG46140 Register Bit Signal Function Register Bit Definition Address 00: 0 01: 25 mV reg<509:508> ACMP1 hysteresis control 10: 50 mV 11: 200 mV 00: 0 01: 25 mV reg<511:510> ACMP0 hysteresis control 10: 50 mV 11: 200 mV 0: off reg<512>...
  • Page 151 SLG46140 Register Bit Signal Function Register Bit Definition Address 000: 0.25x (For single-ended operation only) 001: 0.5x (For single-ended operation only) 010: 1x 011: 2x reg<534:532> ADC PGA gain selection 100: 4x 101: 8x (For single-ended and differential operation) 110: 16x (For differential operation only) 111: Reserved 0: power down 1: power on...
  • Page 152 SLG46140 Register Bit Signal Function Register Bit Definition Address 00: /1 01: /2 reg<561:560> Clock divide ratio control for LF osc 10: /4 11: /16 Matrix power down (matrix_out66)enable for LF oscilla- 0: disable reg<562> 1: enable 0: off reg<563> Low Frequency osc turn on by register 1: turn on (if chip is power down, the LFosc will power down even if it is set to 1)
  • Page 153 SLG46140 Register Bit Signal Function Register Bit Definition Address 000: /1 001:/2 010:/4 011: /3 reg<584:582> clock divide ratio control for ring osc to matrix 100: /8 101: /12 110: /24 111: /64 0: disable reg<585> ADC data synchronized with SPI clock enable 1: enable 0: disable reg<586>...
  • Page 154 SLG46140 Register Bit Signal Function Register Bit Definition Address 0: PWM output duty cycle down to 0% and DCMP out=1 if A>B reg<603> PWM/DCMP1 mode selection 1: PWM output duty cycle up to 100% and DCMP out=1 if A>=B 00: 10 ns 01: 20 ns reg<605:604>...
  • Page 155 SLG46140 Register Bit Signal Function Register Bit Definition Address reg<654> SPI used as ADC/FSM buffer enable (1 clock delayed) 1: enable 0: FSM0[7:0],FSM1[7:0] reg<655> SPI parallel input data source selection 1: ADC reg<656> SPI clock phase (CHPA) refer to SPI spec reg<657>...
  • Page 156 SLG46140 Register Bit Signal Function Register Bit Definition Address LUT4_1 data [bit 14] (if reg<702:701>=11) or CNT2 Val- 0: Reset (CNT value = 0) reg<694> ue Control 1: Set (CNT value = FSM data) 0000: CK_RCOSC 0001: CK_RCOSC_DIV4 0010: CK_RCOSC_DIV12 0011: CK_RCOSC_DIV24 0100: CK_RCOSC_DIV64 0101: DLY_OUT1...
  • Page 157 SLG46140 Register Bit Signal Function Register Bit Definition Address If DLY Mode or Edge Detect: 00: Both Edge 01: Falling Edge 10: Rising Edge 11: None reg<719:718> DLY1 edge mode select If CNT/FSM: 00: Both Edge Reset 01: Falling Edge Reset 10: Rising Edge Reset 11: High level Reset 00: DLY...
  • Page 158 SLG46140 Register Bit Signal Function Register Bit Definition Address register bits from 0 to 15, data delay from 1 to 16 reg<753:750> Pipe Delay out0 selection bits pipes register bits from 0 to 15, data delay from 1 to 16 reg<757:754>...
  • Page 159 SLG46140 Register Bit Signal Function Register Bit Definition Address 00: digital in without schmitt trigger 01: digital in with schmitt trigger reg<781:780> PIN5 input mode control 10: Low Voltage Digital in 11: analog IO 00: 1x push-pull 01: 2x push-pull reg<783:782>...
  • Page 160 SLG46140 Register Bit Signal Function Register Bit Definition Address 00: 1x push-pull 01: 2x push-pull reg<805:804> PIN9 output mode control. 10: 1x open-drain 11: 2x open-drain 00: floating 01: 10 K reg<807:806> PIN9 pull up/down resistor selection 10: 100 K 11: 1 M 0: pull down reg<808>...
  • Page 161 SLG46140 Register Bit Signal Function Register Bit Definition Address 00: digital in without schmitt trigger 01: digital in with schmitt trigger reg<828:827> PIN12 input mode control 10: Low Voltage Digital in 11: analog IO 00: 1x push-pull 01: 2x push-pull reg<830:829>...
  • Page 162 SLG46140 Register Bit Signal Function Register Bit Definition Address reg<863:860> LUT2_3 data Data LUT2_4 or DFF/Latch0 reg<867:864> LUT2_4 Data (if reg<868>=0) or DFF/Latch0 0: DFF function reg<864> DFF/Latch Mode Select 1: Latch function 0: Q output reg<865> DFF/Latch output polarity control 1: QB output 0: initial state is 0 reg<866>...
  • Page 163 SLG46140 Register Bit Signal Function Register Bit Definition Address 0: DFF function reg<915> DFF/Latch Mode Select 1: Latch function 0: Q output reg<916> DFF/Latch output polarity control 1: QB output 0: reset controlled by matrix reg<917> DFF/Latch set or reset selection 1: set controlled by matrix 0: initial state is 0 reg<918>...
  • Page 164 SLG46140 Register Bit Signal Function Register Bit Definition Address 0x: digital output from pin13 reg<999:998> reset output control from pin13 10: reset output from pin13 11: digital output from pin13 PIN2 Reset Control 0: pin2 edge active reg<1000> 1: pin2 high active 0: rising edge reg<1001>...
  • Page 165 SLG46140 24.0 Package Top Marking System Definition Part Code + Assembly Code Date Code + Revision Code Pin 1 Identifier Serial Number Code 000-0046140-111 Page 164 of 169...
  • Page 166 SLG46140 25.0 Package Drawing and Dimensions 14 Lead STQFN FC Green Package 1.6 x 2.0 x 0.55 mm 000-0046140-111 Page 165 of 169...

  • Page 167: Tape And Reel Specifications

    SLG46140 26.0 Tape and Reel Specifications Max Units Leader (min) Trailer (min) Nominal Reel & Tape Part Package # of Package Size Hub Size Width Pitch Length Length Type Pins per Reel per Box Pockets Pockets [mm] [mm] [mm] [mm] [mm] [mm] STQFN...
  • Page 168 SLG46140 27.0 Recommended Land Pattern Units: m 28.0 Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 1.76 mm (nominal). More information can be found at www.jedec.org. 000-0046140-111 Page 167 of 169...

  • Page 169: Revision History

    Updated PGA Specification Conditions 5/31/2017 1.04 Updated POR section Updated Absolute Maximum Conditions and Electrical Characteristics 2/17/2017 1.03 Fixed typos Updated Silego Website & Support 1/18/2017 1.02 Updated Section Programmable Delay / Edge Detector Fixed typos 10/25/2016 1.01 Fixed typos 10/20/2016 1.00...
  • Page 170 Customers can contact their local sales representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. More information regarding your local representative is available at the Silego website or send a request to info@silego.com...

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