Yamaha ICP1 Service Manual page 26

H G
Q Q
3 7 6 3 1 5 1 5 0
BLOCK DIAGRAM
T E
L 1 3 9 4 2 2 9 6 5 1 3
CN101
Switch x 10
LED x 10
PN
w w w
.
F E
DM
X101
16MHz
+VCC INT +3.3D
xtal/extal
CKIO (64Mhz)
CPU
/CS3, CPUA[2-14], RD/nWR,
HD6417727F160C
/WRLL, /WRLH, /WRHL, /WRHH,
Int.128MHz / Ext.64MHz
CKE, /RAS3L, /CAS
Clock Mode:2 (Xtal.x4)
Area 0 Bus 16bit
Endian Big Endian
IC104
240P
+3.3D –VEE
CN301
LCDCL1, CL2, DATA[0-3], _FLM, M_DISP
+3.3D +5D –VEE
VADJ Control
NJM4556
IC301 8P
LCD_VADJ, CTRL
TR301, 302
+5D
LCD BL
ON/OFF
LCD_ON
TR303
TR304
CN201
SWIN[0-10]
Switch Scan
Driver
SWSCAN
DTC144E
TR201
LED
Driver
DTC123J ENENBL
SCN_LD
TR202
ENINA,B
Hub, DME24/64N
x a o
y
i
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D
8
+3.3D
+3.3D +3.3D
64Mbit 64Mbit
SDRAM FLASH
IC106 IC107
86P 48P
32bit /CS0, CPUA[1-22], 16bit
/WRLL, /RD,
CPUD[0-31] CPUD[0-15]
/RESET
(–11.8D)
–VEE
DC-DC
M5291
(+1.9D)
IC303 8P
+VCC_INT
Power Regulator Power Regulator
PQ070XZ01 PQ033Y3H3
IC201 5P IC202 5P
+3.3D
+3.3D
Ethernet
16bit CPUD[0-15] Controller
S1S60000
Q Q IC402
/RD, /WRLH, CPUA[1-2]
3 7 6 3
100P
/IRQ_ENET
Microwire
+5D
EEPROM
93LC46B
IC404
8P
/RST_ENET
+3.3D +5D
EIN Latch
VHC14, 74
IC304 14P
IC302 14P
DATA Encoder
EC301
ICP1 ADAPTOR BOX
ICP1
JK202
JK203
PW
JK201
u 1 6 3
DC IN
16V(PA-300)
.
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C B
2 4
9 9 8
SYSTEM RESET
/RESET
S-80130ANMC
IC103
5P
+3.0V detection, 50ms delay
DC-DC PWR
LM2673
IC203 7P
+5D
+3.3D
X401
25MHz
+3.3D
MII
PHY ±
TX
ICS1893
IC406
±
64P RX
1 5 1 5 0 8 9 2 4
OSCO(25MHz)
RJ-45
JK401
Power Over Ethernet
m
c o
A
2
9 9 ICP1
2
3
4
9 8 2 9 9
5
6
28CA1-8832059 2
3
BLOCK DIAGRAM