Sony KLV-S23A10E Service Manual page 65

A B C
N.-WAX
1
+3V3D
R3801
1k
1/16W
2
C3800
0.1
10V
3
R3831
100
nBOARD_RST
C3811
470p
50V
JIG_MODE
4 nCI_OVR
nMODEM_OVR
nSMC_INT
nFTV2005_SEL
FTV_CONFIG0
FTV_CONFIG1
FTV_CONFIG2
5
R3822 R3824 R3825 R3836 R3837
10k
10k 10k 10k 10k
6
7
nFTV2005_SEL
FTV_CONFIG0
FTV_CONFIG1
FTV_CONFIG2
8
+3V3D
FB3803
0uH
C3814
0.1
10V
2SA2029T2LQ/R
NVM_RST
9
NVM_WP
SCL_N
SDA_N
10
11
D E F
RESET SIGNAL GENERATION
R3800
nDAMON_RST
22k
D3800
1PS184-115 1/16W
0
R3832
nMASTER_RESET
C3801
0.1 10V
C3802
10
16V
nSW_FE_RESET
GND OUT
Vcc
CD
R3803
100
IC3800
PST3629UL
nMASTER_RESET
RESET IC
+3V3D
+3V3D
R3847
Q3800
Q3806 XX
R3862 R3841
DTC114EKA-T146
4.7k 10k
2SC5658T2LQ/R
1/16W
1/16W
nNAND_WP
R3846
470
Q3805
1/16W
DTC114EKA-T146
nFE_RESET
GP INPUT TO EMMA
R3809 100
PPORT3
R3815 100
PPORT0
R3806 100
PPORT1
R3810 100
PPORT4
R3818 100
PPORT2
R3852 100
PPORT44
R3861 100
PPORT12
PPORT13
R3830
100
+3V3D
R3838 R3840 R3848
10k 10k 10k
R3849 100
PPORT42
R3853 100
PPORT45
R3854 100
PPORT46
R3855 100
PPORT47
R3856 100
PPORT48
100
R3857
SPKRB
R3858 100
STSCHGB
VS2B
R3859
100
+3V3D S/W OPTION SELECT R's
nRESET
R3802
100
C3803
THIS RESISTOR AND
XX
R3894 R3896
CAPACITOR TO BE PLACED
XX 10k
CLOSE TO IC3801 AND IC3802
R3898 R3892
10k
XX
R3895 R3897
10k XX
R3899 R3893
XX
10k
EEPROM
Q3808
R3851
XX
IC3807
R3850 M24128-BWMN6T(A)
EEPROM
1k
SD
C3816 VCC
0.1
TEST !S1!
R3843 100
S2
SCL
100
R3844
SDA VSS
100
R3842
SDA_COFDM
FB3805 0uH
SCL_COFDM
FB3806 0uH
G H I
+3V3D
FB3801
0uH
IC3805
74LVC08APW
QUAD AND GATE C3810
R3839 R3827 C3809
1k 1k 0.1 0.1
10V 10V
1A VDD 1/16W
1B 4B
1Y 4A
2A 4Y
2B
3B
2Y 3A
GND 3Y
GCSB2
R3828 100
R3829 XX
Q3804 IC3806
DTC114EKA-T146 TC7SH08FU(T5RSOYJF)
2 I/P GATE AND
A Vcc
GCSB0 B
GND Y
+3V3D_81
+3V3D
FB3800
0uH
C3804 C3805
0.1
0.1
10V 10V
VCC
!CL!
1Q 8Q
CI_PWR_EN
8D
1D RDATA[15]
RDATA[8]
2D 7D
RDATA[14]
RDATA[9]
2Q 7Q
MODEM_DTR MODEM_EN
6Q
3Q
CI_BYPASS
3D 6D
RDATA[10] RDATA[13]
5D
4D
RDATA[12]
RDATA[11]
4Q 5Q
CLK
GND
IC3801
74LVC273PW
GP OUTPUT
SIGN11532
C3806
0.1
10V
IC3802
74LVC273PW
OCTAL D-TYPE
FLIP/FLOP
VCC
!CL!
1Q 8Q
FASTBLK_GPIO CI_EN
8D
1D
RDATA[0]
RDATA[7]
2D 7D
RDATA[1] RDATA[6]
7Q
2Q
3Q 6Q
NVM_WE nSW_FE_RESET
6D
3D
RDATA[2]
RDATA[5]
4D 5D
RDATA[3] RDATA[4]
5Q
4Q
PCCARD_EN NVM_RST
GND CLK
+3V3D
R3804
2.2k
CHIP
RDATA[0-15]
Q3801
DTC114EKA-T146
N
7/7
- 65 -
J K L M
nCI_EN
nPC_EN
nCIPC_EN
nCI_WAIT
nRDY_DAMON
GRDYB
IC3803
TC7SH08FU(T5RSOYJF) +3V3D
FB3804
2 I/P GATE AND
0uH
A VCC
B
C3812 C3817
0.1 0.1
GND Y
10V 10V
nRESET
nFE_RST
+3V3D
FB3802
0uH
C3807 C3813
0.1 0.1
10V
10V
+3V3D
PLACE CLOSE TOGETHER
100
R3816
CI_PWR_EN <- RDATA[15]
R3826 100
MODEM_EN <- RDATA[14]
R3817 100
CI_BYPASS <- RDATA[13]
R3805 XX
GPO_CLK
R3808 XX
XX
R3813
R3823 XX
100
R3814
<- RDATA[8]
nSMC_RST
R3820 100
<- RDATA[7]
CI_EN
R3807 XX
R3835 100
<- RDATA[5]
nSW_FE_RESET
NVM_RST <- RDATA[4]
R3821 100
<- RDATA[3]
PCCARD_EN
R3819 100
NVM_WP <- RDATA[2]
R3834 XX
R3860 XX
IC3804
74LVC32A-PW +3V3D_81
QUAD 2 I/P OR GATE
RADD[0-25]
GCSB0
1A Vcc
RADD[14]
C3808
1B 4B 0.1
10V
4A
1Y
2A 4Y
FWEB
2B 3B
3A
2Y
GND 3Y
FOEB
COMPONENTS MARKED AS XX ARE NOT FITTED ON THIS MODEL
~ N Board Schematic Diagram [ MPEG2 Decoder ] Page 7/7 ~
N O
GPO_CLK