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United Electronic Industries PowerDNA DIO-403 User Manual

48-channel digital i/o layer for the powerdna cube
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PowerDNA DIO-403 User Manual
48-channel Digital I/O layer
for the PowerDNA Cube
February 2013 Edition
PN Man-DNA-DIO-403-0213
Version 4.4
© Copyright 1998-2013 United Electronic Industries, Inc. All rights reserved.
United Electronic Industries, Inc.
Version 3.3

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Summary of Contents for United Electronic Industries PowerDNA DIO-403

  • Page 1 PowerDNA DIO-403 User Manual 48-channel Digital I/O layer for the PowerDNA Cube February 2013 Edition PN Man-DNA-DIO-403-0213 Version 4.4 © Copyright 1998-2013 United Electronic Industries, Inc. All rights reserved. United Electronic Industries, Inc. Version 3.3...
  • Page 2 PowerDNA DIO-403 Layer No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form by any means, electronic, mechanical, by photocopying, recording, or otherwise without prior written permission. Information furnished in this manual is believed to be accurate and reliable.

  • Page 3: Table Of Contents

    PowerDNA DIO-403 Layer -ii- Table of Contents Introduction ..................iii Organization of this manual ..........iii Conventions ................iv 1 The DIO-403 Layer ................1 Device architecture ..............2 Layer capabilities ..............2 Layer connectors and wiring ..........3 2 Programming using the UeiDaq Framework ........5 Creating a session ..............

  • Page 4: Introduction

    This document outlines the feature-set and use of the DIO-403 layer. This layer is a digital input and output module for the PowerDNA I/O Cube. Organization of this manual This PowerDNA DIO-403 User Manual is organized as follows: Introduction This chapter provides an overview of PowerDNA Digital Input Series board features, the various models available and what you need to get started.

  • Page 5: Conventions

    PowerDNA DIO-403 Layer -iv- Conventions To help you get the most out of this manual and our products, please note that we use the following conventions: Tips are designed to highlight quick ways to get the job done, or reveal good ideas you might not discover on your own.

  • Page 6: The Dio-403 Layer

    PowerDNA DIO-403 Layer The DIO-403 Layer The DIO-403 is a 48-line digital I/O layer that operates at TTL levels. Features:  Onboard FIFO memory: 128 32-bit words input / 128 32-bit words output  Pattern output, I/O throughput rate is 10k samples/sec (20k aggregate) ...

  • Page 7: Device Architecture

    PowerDNA DIO-403 Layer 1.1 Device architecture Architecturally, the DIO-403 is divided into a non-isolated logic part and an isolated part with I/O buffers. Every line is protected from overvoltage and electrostatic discharge by a Harris SP720 overvoltage & ESD electronic protection array. One 22Ω current limiting resistor limits current in every line.

  • Page 8: Layer Connectors And Wiring

    PowerDNA DIO-403 Layer 1.3 Layer connectors and wiring Wiring of DIO-403 is very simple. The user should wire input and output lines relative to DGND.  TRIGx line is an input for external trigger. United Electronics Industries, Inc. www.ueidaq.com Tel: 781-821-2890...

  • Page 10: Programming Using The Ueidaq Framework

    PowerDNA DIO-403 Layer 2 Programming using the UeiDaq Framework This section describes how to program the PowerDNA DIO-403 using the UeiDaq’s framework API. The UeiDaq framework is object oriented and its objects can be manipulated in the same manner from different development environments such as Visual C++, Visual Basic or LabVIEW.

  • Page 11: Reading Data

    PowerDNA DIO-403 Layer The following sample shows how to configure the simple mode. Please refer to the “UeiDaq Framework User’s Manual” to learn how to use the other timing modes. session.ConfigureTimingForSimpleIO(); 2.4 Reading data Reading data from the DIO-403 is done by using a reader object.

  • Page 12: Programming Using The Low-Level Api

    PowerDNA DIO-403 Layer Programming using the Low-Level API This section describes how to program the PowerDNA cube using the low-level API. The low-level API offers direct access to PowerDNA DAQBios protocol and also allows you to access device registers directly.

  • Page 13: Channel List Settings

    PowerDNA DIO-403 Layer Adding these bits into configuration word causes layer to switch respective ports into outputs. 3.3 Channel list settings Channel list is not currently supported for this layer. 3.4 Layer-specific commands and parameters There are three layer-specific function used to access and control the state of I/O lines: ...

  • Page 14: Using Layer In Dmap Mode

    PowerDNA DIO-403 Layer 3.6 Using layer in DMap mode #include "PDNA.h" 1. Start DQE engine #ifndef _WIN32 DqInitDAQLib(); #endif // Start engine DqStartDQEngine(1000*10, &pDqe, NULL); // open communication with IOM DqOpenIOM(IOM_IPADDR0, DQ_UDP_DAQ_PORT, TIMEOUT_DELAY, &DQRdCfg); // Set hysteresis at this point DqAdv40xSetHyst(hd0, DEVNIN, 0x132, 0x2CA);...
  • Page 15 PowerDNA DIO-403 Layer -10- DqeSetEvent(pBcb, DQ_eDataAvailable|DQ_ePacketLost|DQ_eBufferError|DQ_ePacketOOB); 4. Start operation DqeEnable(TRUE, &pBcb, 1, FALSE); 5. Process data while (keep_looping) { DqeWaitForEvent(&pBcb, 1, FALSE, timeout, &eventsin); if (eventsin & DQ_eDataAvailable) { datarcv++; printf("\ndata %08x ", *(uint32*)ioffset); *(uint32*)ooffset = datarcv; 6. Stop operation DqeEnable(FALSE, &pBcb, 1, FALSE);...

  • Page 16: Appendix

    PowerDNA DIO-403 Layer -11- Appendix Appendix A - Accessories The following cables, boards, and layers are available for the DIO-40x layer. DNA-CBL-62 2.5ft, 62-way round shielded cable; for connection to panel(s) DNA-DIO-O22 Accessory panel for PowerDNA DIO layers; panel distributes 24 DIO channels into single group of 24 lines or, in case with 48 DIO channels, into 3 groups of 16 lines which connect to three Opto-22 compatible connectors.

  • Page 18: Glossary

    PowerDNA DIO-403 Layer -13- Glossary Application Programming Interface, a collection of high-level language function calls that provide access the functions in a driver or other utility. One binary digit, either 0 or 1. byte Eight related bits of data, an 8-bit binary number.
  • Page 19 PowerDNA DIO-403 Layer -14- integral control A control action that eliminates the offset inherent in proportional control. isolation voltage The voltage that an isolated circuit can normally withstand, usually specified from input to input and/or from any input to the amplifier output, or to the computer bus.
  • Page 20 PowerDNA DIO-403 Layer -15- output slew rate The rate of change of an analog output voltage from one level to another. overhead The amount of computer processing resources, such as time or memory, required to accomplish a task. PID control A 3-term control algorithm combining proportional, integral and derivative control actions.
  • Page 21 PowerDNA DIO-403 Layer -16- single-ended a term used to describe an analog-input configuration where you measure each channel with respect to a common analog ground. S/s, S/sec samples/sec, samples per second system noise A measure of the amount of noise seen by an analog circuit or an A/D when the analog inputs are grounded.

  • Page 22: Index

    PowerDNA DIO-403 Layer - Index -17- Index Advanced Circular Buffer ....8 mode architecture ........2 ACB ..........8 DMap .......... 9 buffer(s)........... 2 over-voltage protection ....1 data & word size ......7 programming (low level) commands ........8 layer configuration ......

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