Site Preparation and Installation ..................... 14 Docking the TFRAME to the V93000 testhead ................14 Ethernet Connections and IP Addressing .................. 15 Software installation when controlling AT93000 via V93000 Smartest ........15 Customer Loadboard ....................... 15 Appendix: Example Customer Documentation ................. 16 Appendix: Software installation when controlling AT93000 via PC ..........
Figure 1: V93000 CTH testhead with Multilane TFRAME attached on top ........ 5 Figure 2: Building blocks of the Multilane TFRAME ..............5 Figure 3: TFRAME with red arrows pointing to the 4 Multilane cassettes ......... 6 Figure 4: AT93000 signal paths from instruments to DUT ............6 Figure 5: Instrument Cassette with protective cover removed..........
V93000 ATE Test Solutions | MultiLane (multilaneinc.com) Figure 1, the AT93000 twinning frame (TRAME) is hard docked on top of a V93000 test head. The AT93000 is compatible with CTH and STH Advantest V93000 testheads. The user’s DUT loadboard is hard docked on top of the TFRAME and the device handler or wafer prober is hard docked to the DUT loadboard.
The main advantage of the ATE system as compared to using benchtop instruments, is that the signal path between DUT and Cassette instruments is considerably shorter thus minimizing insertion and return losses. The AT93000 channel density maximum is up to 32 channels if all 4 cassettes are fully populated.
Figure 5: Instrument Cassette with protective cover removed Figure 6 shows the AT93000 area located under the docked device loadboard. Figure 6: AT93000 Cassette Area Item Description of Items in Figure 6 See: Figure 5: Instrument Cassette with protective cover...
Clock Sync Configuration on AT93000 backplanes” on page 9. Figure 7: (Top View) AT93000 Backplane and Cassette numbering Figure 8: Pogo Block, ordered through Advantest. Part number E8028-PSD A subset of these quadrants brings the V93000 resources up to the loadboard. Advantest P/N E8028-PSD...
“clock-in” SMP connectors on the backplane having the slaved instruments, using two high-speed cables. Check Multilane instrument datasheets for maximum clock sync frequency. For explanation how to send DUT clock signals to the ML backplanes via family board, see Multilane Family Board Documentation.
The switch straps are for Multilane internal use only and should never be changed from what is shown in Figure 10. Figure 10:SPMP Clock Connectors on ML Backplanes 1 and 2 The ML backplane SMPM connectors are shown in lower left picture of Figure 10.
1. Manually: Set each switch to either 3V3 or GND 2. USB Programming Mode: Set all switches to PRG Setting Master/Slave Manually Set the 5 switches on each backplane using Figure 1Figure 12 and the table in Figure 13. U450 U451 U452 U453...
Figure 14: Backplane USB and Master/Slave LED light indicators Setting Master/Slave using USB Programming Mode Contact Multilane if USB Programming Mode is to be used. Step 1: Set all switches to PRG Step 2: Connect laptop to USB port shown in...
Figure 15:GUI for Master/slave config. Family Board The Multilane family board, AT93000-1900002, is a general-purpose solution and is optimized for high-speed devices with lower digital pin counts and lower current requirements. If this Family board does not suit your application and you require a different selection of V93000 tester resources, a custom family board will have to be designed.
(multilaneinc.com) Docking the TFRAME to the V93000 testhead The AT93000 weighs approximately 35Kg, so some type of mechanical lift assist may be required. For additional information on using a mechanical lift to assist with docking the TFRAME, refer to Advantest Service Documentation, Topic 342435, “Lifting the Twinning equipment”.
Ethernet Connections and IP Addressing Multilane instruments are controlled by individual IP addresses. IP addresses are hardcoded and are not dynamically assigned at runtime (DHCP). For help choosing the appropriate ethernet connections for each instrument, contact Multilane at ATE-FAE@multilaneinc.com Software installation when controlling AT93000 via V93000 Smartest Refer to the site preparation manual at V93000 ATE Test Solutions | MultiLane (multilaneinc.com)
Appendix: Example Customer Documentation Here is documentation that Multilane uses to guarantee consistent customer configurations leaving our factory. Items in RED are unique for each assembly. The items in RED here are an example and should be changed to match the customer’s assembly requirements...
Appendix: Software installation when controlling AT93000 via PC The AT93000 can also be controlled via a PC by connecting the Ethernet ports to the PC PC minimum hardware requirements are as follows: • Windows XP SP3 or greater • Minimum 2 GB RAM •...
Appendix: Older Revision Backplane Clock Jumper Settings (AT4000 REV B) The AT4000 REV B backplane uses jumpers instead of switches to control MASTER/SLAVE clock selection. Figure 17:AT4000 REV B Backplane Figure 18:AT4000 REV B cable connection options between backplanes To set MASTER/SLAVE, refer to the following table: U450 is U451 is U452 is...
Page 19
Rev. No. Amendments Revision date Section Description Initial revision uploaded to Multilane website 0.9.1 Added appendix “Loadboard reference designators” Jan 14 2021 Added cassette #’s 0.9.2 Changed U13 to “0” for “ALL SLAVE” configuration March 2, 2021 0.9.3 Appendix 4...
Need help?
Do you have a question about the AT93000 and is the answer not in the manual?
Questions and answers