Contents Contents...........................3 Table of Figures........................4 Purpose of this User Manual .....................5 System Nomenclature.......................5 Items used for diagnostics......................6 Quick checks before running hardware diagnostics..............6 Ping Check..............................6 Docking Checks .............................. 6 Twinning Frame Cables Routing Checks......................6 SMPM connector checks..........................7 Faceplate Checks............................
Purpose of this User Manual The purpose of this User Manual is to help isolate Multilane-related failure mechanisms inside the AT93000 twinning frame shown in Figure Figure 1: AT93000 internal view System Nomenclature The cassette and backplane numbering are shown in Figure 2. The V93000 digital pogo block locations are also noted in this figure.
Docking Checks See Advantest manuals for proper docking procedures. Is AT93000 Twinning Frame properly docking to V93000? Is DUT Loadboard properly docking to AT93000? This can be done manually or using the Advantest docking remote control. Twinning Frame Cables Routing Checks Checking the cable routing do not get pinched by the bridge beam (every service engineer should have a 3D printed bridge beam to check this).
Are all SMPM male connectors on the loadboard stiffener straight? Make sure none are bent. Figure 3. Are all SMPM female connectors on the Multilane cassettes free of dirt and in good condition? Figure 4. Figure 3: SMPM male connectors on...
Faceplate Checks Refer to Figure 5. Are Power, Ethernet and Air Supply securely attached to AT93000 faceplate? Is 12V power plugged into test floor outlet and power supply switch turned on? o Switch is on backside of 12V power supply box.
In Example 3 above, an external source must be used to perform DSO Rx diagnostics. The diagnostic GUI supports the following Multilane benchtop instruments that can be used as sources; however, cabling to the DSO Rx backplane should be done with the assistance of Multilane support. External...
Diagnostic GUI When the GUI is opened, three options are available: “Load from Model File”, “Skip”, and “Create a Model File”. 1. Load from Model File: allows the user to browse a previously made Model File containing the instruments info including IP addresses in order to run diagnostics with a simple click. One can always manually add additional instruments.
Module Settings In module settings the user will be able to detect the instrument’s temperature in addition to the board revision, FW revision, calibration, IP address, supported FW options, and others, as shown in Figure 9. Figure 9: Module Settings Monitor In the monitor section, the user can track the different settings applied to the BERT including the amplitude, pre- and post- emphasis, 7 taps, Tx and Rx pattern, and others, as shown in...
Loopback In loopback section, the user first must “initialize” in order to generate a signal from the BERT. The GUI will specify what settings are being set, and it can be also tracked in the Monitor section. After initialization, a refresh button should be clicked to get latest BER and SNR values.
Module Settings In module settings the user will be able to detect the instrument’s temperature in addition to the board revision, FW revision, FPGA revision, IP address, supported FW options, calibration coefficients (by clicking “Load Calibration”), and others, as shown in Figure 12. Figure 12: Module Settings Monitor In the monitor section, the user will be able to detect Eye diagrams of the signal coming from...
Figure 14: Monitor - Eye Diagrams AT-BERT and AT-DSO The user can connect to as many BERTs and DSOs as needed using the Diagnostic GUI. By that, one should refer to the Loopback section of the BERT to generate a signal and detect it on the Monitor section of the DSO.
Cable: 1x1 38cm, SMPM-BM(f) <-> 2 (ship as matched Red Lines 1.85mm(f) pairs) Figure 15: AT93000-POGO All of the instruments datasheets and user manuals are available on MultiLane NOTES: website. Refer to the System User Manual for clock routing. Refer to the Diagnostic Kit Manual for cables routing.
In addition to the previous, the following can also be done as seen in Figure 20: NOTES: 1. Add model file description 2. Specify the calibration status of the BERT: OFF, Factory, or custom by writing the path of the calibration file extracted from the ATE Calibration GUI available on MultiLane website. Figure 19: Model-Editor...
Appendix II: Change IP address, Firmware and FPGA Changing the IP Address Launch ATE-Diagnostic Select the start button iii. Select the instrument to change the IP address: Write the device Name, and the corresponding IP address, and select the type (BERT, DSO, AWG). Select the Add button.
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After connecting to the instrument, the red circle will turn green. Click on the refresh button to check the device settings. Right-click on the device name and click on the Maintenance Tool to change the IP address, Network Mask, or Gateway; apply write.
NOTES: to AT1000. Updating the Firmware: Contact MultiLane ATE Support to make sure you have the right Firmware file before programming. If the wrong Firmware is programmed onto a device, it could potentially break the unit. Select Firmware Select a USB cable to connect.
Updating the FPGA: Installing the wrong FPGA has a high chance to break the unit, which MultiLane is not liable for. Please confirm with the MultiLane team before proceeding to make sure you have the right FPGA file before programming.
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Load the latest FPGA program iii. Upload the latest FPGA program The unit reconnect then needs to be power cycled via the Diagnostic GUI, and the fact that the FPGA is reading as the updated version confirmed. Do not skip this step.
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