Holtek HT82M75REW Manual

2.4ghz transceiver 8-bit otp mcu

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Features
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General Description
The device is an 8-bit high performance, RISC architec-
ture microcontroller devices specifically designed for
multiple I/O, mouse/keyboard appliances and SPI con-
trol product applications. The advantages of low power
consumption, I/O flexibility, Timer functions, Watchdog
Rev. 1.00
Downloaded from
Elcodis.com
electronic components distributor
Operating voltage:
f
= 6MHz: 1.8V~3.3V
SYS
Internal 6MHz RC oscillator for f
SYS
Power down and wake-up functions to reduce
power consumption
Two bit to define microcontroller system clock
(f
/1, f
/2, f
/4)
SYS
SYS
SYS
All instructions executed in one or two machine
cycles
Table read instructions
63 powerful instructions
6-level subroutine nesting
Bit manipulation instruction
Program Memory: 4K´15
Data Memory: 128´8~160´8
Watchdog Timer function
HT82M75REW/HT82K75REW
2.4GHz Transceiver 8-Bit OTP MCU
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Up to 40 bidirectional I/O lines with pull-high options
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All I/O pins have falling and rising edge wake-up
function
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Single 16-bit internal timer with overflow interrupt
and timer input
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Low voltage reset function (LVR) for DC_DC output
controlled by configuration option
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Built-in DC/DC to provide stable 2.8V, 3.0V, 3.3V
with error ±5% selected by configuration options
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Low voltage detector (LVD) with levels
1.8V/2.0V/2.2V/2.5V/2.8V ±5% for battery input
(BAT_IN) selected by application program
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Wide range of available package types
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EEPROM Memory with 128´8 capacity
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RF Transceiver with 2.4GHz RF frequency
timer, Power Down, wake-up functions together with the
optional peripherals such as EEPROM Memory and RF
transceiver provide the devices with versatility for indus-
trial control, consumer products, subsystem controllers,
RF module control, etc.
1
June 11, 2010

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Summary of Contents for Holtek HT82M75REW

  • Page 1 HT82M75REW/HT82K75REW 2.4GHz Transceiver 8-Bit OTP MCU Features · · Operating voltage: Up to 40 bidirectional I/O lines with pull-high options = 6MHz: 1.8V~3.3V · All I/O pins have falling and rising edge wake-up · Internal 6MHz RC oscillator for f function ·...
  • Page 2: Selection Table

    1. There are additional peripherals named RF Transceiver with RF frequency of 2.4GHz and Data EEPROM with capacity of 128 bytes in HT82M75REW and HT82K75REW devices. All information related to the RF Transceiver and EEPROM Data Memory will be described in the corresponding section respectively.
  • Page 3: Pin Description

    HT82M75REW/HT82K75REW Pin Description The following table only includes the pins which are directly related to the MCU. The pin descriptions of the additional peripheral functions are located at the corresponding section of the datasheet along with the relevant peripheral func- tion functional description.
  • Page 4 HT82M75REW/HT82K75REW Pin Description for EEPROM Memory Pin Name Type Description ¾ VDDP External Positive power supply for EEPROM Memory ¾ VSSP External Negative power supply for EEPROM Memory, ground Internal Serial data input/output signal Internal connected with MCU I/O line.
  • Page 5: Absolute Maximum Ratings

    (2) The pin descriptions for all external pins except the RF Transceiver pins listed in the above table are de- scribed in the preceding MCU section. (3) The INT and RST lines are internally connected to the MCU I/O pins PC2 and PC3 respectively for the HT82M75REW and HT82K75REW devices. Absolute Maximum Ratings -0.3V to V Supply Voltage ......V...
  • Page 6 HT82M75REW/HT82K75REW D.C. Characteristics for EEPROM Memory Ta=-40°C~85°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions ¾ ¾ Operating Current Read at 100kHz ¾ ¾ Operating Current Write at 100kHz ¾ ¾ =0 or V Standby Current STB* ²*² The operating current ICC1 and ICC2 listed here are the additional currents consumed when the EEPROM Note: Memory operates in Read Operation and Write Operation respectively.
  • Page 7: Power-On Reset Characteristics

    HT82M75REW/HT82K75REW A.C. Characteristics for EEPROM Memory Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions ¾ System Clock ¾ ¾ ¾ Watchdog OSC Period RCSYS Watchdog Time-out Period with ¾ ¾ WDTS=1 4.57 WDT1 6-stage Prescaler ¾ ¾ ¾...
  • Page 8 HT82M75REW/HT82K75REW RF Transceiver D.C. Characteristics =3V, Ta=25°C Symbol Test Conditions Min. Typ. Max. Unit DC-DC ¾ RF Transceiver TX Active. At 0 dBm output power Off* DC-DC ¾ RF Transceiver RX Active in Normal Mode (250 Kbps) Off* DC-DC ¾...
  • Page 9 HT82M75REW/HT82K75REW Transmitter =3V, Ta=25°C, LO frequency=2.445GHz, 250 Kbps, DC-DC Off Parameters Test Conditions Min. Typ. Max. Unit ¾ ¾ RF carrier frequency 2.400 2.495 ¾ Maximum RF output power At 0 dBm output power setting ¾ ¾ ¾ ±4 RF output power Accuracy ¾...
  • Page 10: System Architecture

    A key factor in the high-performance features of the execution functions. In this way, one T1~T4 clock cycle Holtek range of microcontrollers is attributed to the inter- forms one instruction cycle. Although the fetching and nal system architecture. The devices take advantage of...
  • Page 11 HT82M75REW/HT82K75REW When executing instructions requiring jumps to writeable. The activated level is indexed by the Stack non-consecutive addresses such as a jump instruction, Pointer, SP, and is neither readable nor writeable. At a a subroutine call, interrupt or reset, etc., the...
  • Page 12: Program Memory

    HT82M75REW/HT82K75REW Arithmetic and Logic Unit - ALU offer users the flexibility to freely develop their applica- tions which may be useful during debug or for products The arithmetic-logic unit or ALU is a critical area of the requiring frequent upgrades or program changes. OTP...
  • Page 13 HT82M75REW/HT82K75REW ¨ The three methods are shown as follows: The in- will not be enabled until the TBLH has been backed structions ²TABRDC [m]² (the current page, one up. All table related instructions require two cycles to complete the operation. These areas may function as...
  • Page 14 HT82M75REW/HT82K75REW tempreg1 ; temporary register #1 tempreg2 ; temporary register #2 a,06h ; initialise table pointer - note that this address ; is referenced tblp,a ; to the last page or present page tabrdl tempreg1 ; transfers value in table referenced by table pointer ;...
  • Page 15: Data Memory

    HT82M75REW/HT82K75REW Data Memory The Data Memory is a volatile area of 8-bit wide RAM General Purpose Data Memory internal memory and is the location where temporary in- All microcontroller programs require an area of formation is stored. Divided into two sections, the first of...
  • Page 16 HT82M75REW/HT82K75REW H T 8 2 M 7 5 R E W H T 8 2 K 7 5 R E W 0 0 H I A R 0 0 0 H I A R 0 0 1 H 0 1 H...
  • Page 17: Special Function Registers

    HT82M75REW/HT82K75REW Special Function Registers To ensure successful operation of the microcontroller, pair, IAR0 and MP0 can together only access data from certain internal registers are implemented in the Data Bank 0, while the IAR1 and MP1 register pair can ac- Memory area.
  • Page 18 HT82M75REW/HT82K75REW Accumulator - ACC Otherwise, the configuration option TBHP is disabled, the instruction ²TABRDC [m]² reads the ROM data as The Accumulator is central to the operation of any defined by TBLP and the current program counter bits. microcontroller and is closely related with operations carried out by the ALU.
  • Page 19: Input/Output Ports

    Input/Output Ports tine can change the status register, precautions must be Holtek microcontrollers offer considerable flexibility on taken to correctly save it. their I/O ports. With the input or output designation of ev-...
  • Page 20 HT82M75REW/HT82K75REW P u l l - H i g h C o n t r o l B i t O p t i o n W e a k D a t a B u s P u l l - u p...
  • Page 21: Timer/Event Counters

    Timer Control Register - TMRC The system clock divided by 4 is used when the timer is in the timer mode or in the pulse width measurement The flexible features of the Holtek microcontroller mode. Timer/Event Counters enable them to operate in three...
  • Page 22 HT82M75REW/HT82K75REW Configuring the Timer Mode registers control the full operation of the Timer/Event Counter. Before the timer can be used, it is essential In this mode, the timer can be utilised to measure fixed that the TMRC register is fully programmed with the...
  • Page 23 HT82M75REW/HT82K75REW Configuring the Event Counter Mode start counting until the PA2/TMR pin returns to its origi- nal high level. At this point the TON bit will be automati- In this mode, a number of externally changing logic cally reset to zero and the timer will stop counting. If the...
  • Page 24 HT82M75REW/HT82K75REW I/O Interfacing When the Timer/Event Counter is read, or if data is writ- ten to the preload register, the clock is inhibited to avoid The Timer/Event Counter, when configured to run in the errors, however as this may result in a counting error, event counter or pulse width measurement mode, re- this should be taken into account by the programmer.
  • Page 25 HT82M75REW/HT82K75REW Timer Program Example This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are en- abled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit.
  • Page 26 HT82M75REW/HT82K75REW Timer/Event Counter Interrupt condition in the interrupt control register until the corre- sponding interrupt is serviced or until the request flag is For a Timer/Event Counter interrupt to occur, the global cleared by a software instruction. interrupt enable bit, EMI, and its corresponding timer in- It is recommended that programs do not use the ²CALL...
  • Page 27 The most fundamental and unavoidable reset is the More information regarding external reset circuits is one that occurs after power is first applied to the located in Application Note HA0075E on the Holtek microcontroller. As well as ensuring that the Program website.
  • Page 28 HT82M75REW/HT82K75REW · Low Voltage Reset - LVR Reset Initial Conditions The microcontroller contains a low voltage reset cir- The different types of reset described affect the reset cuit in order to monitor the supply voltage of the de- flags in different ways. These flags, known as PDF and vice.
  • Page 29 HT82M75REW/HT82K75REW The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers.
  • Page 30 Power Down Mode and Wake-up Power Down Mode Wake-up All of the Holtek microcontrollers have the ability to enter After the system enters the Power Down Mode, it can be a Power Down Mode. When the device enters this woken up from one of various sources listed as follows: mode, the normal operating current, will be reduced to ·...
  • Page 31: Watchdog Timer

    HT82M75REW/HT82K75REW finally enabled or when a stack level becomes free. The ternal WDT oscillator and its clock period may vary with other situation is where the related interrupt is enabled VDD, temperature and process variation. The WDT and the stack is not full, in which case the regular inter- clock is further divided by an internal 6-stage counter rupt response takes place.
  • Page 32 HT82M75REW/HT82K75REW Bit No. Func. Name R/W Description 0: MCU wakeup not by period counter CNT_WK 1: MCU wakeup by period counter overflow (Read only) This bit is used to decide whether the DC block is in operation DC_Ctrl 0: enable DC_DC output (default) 1: disable DC_DC output Flag for 2.2V battery low signal coming from DC/DC block (error ±5%)
  • Page 33 HT82M75REW/HT82K75REW DC-to-DC Converter (DC/DC) Section ting of the configuration option and software control bit as mentioned above, then the LVR still works even if the This circuit is used to generate a stable 2.8V or 3.0V or MCU enters into the Power Down Mode. It is recom- 3.3V (error±5%) power voltage for whole IC and output...
  • Page 34 HT82M75REW/HT82K75REW SPI Serial Interface The device includes one SPI Serial Interfaces. The SPI The SPIR register is used to select SPI mode, clock po- interface is a full duplex serial data link, originally de- larity edge selection and SPI enable or disable selec- signed by Motorola, which allows multiple devices con- tion.
  • Page 35 HT82M75REW/HT82K75REW D a t a B u s S B D R ( R e c e i v e d D a t a R e g i s t e r ) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0...
  • Page 36 HT82M75REW/HT82K75REW SPI Operation collision error has occurred so return to step5. If equal to zero then go to the following step. All communication is carried out using the 4-line inter- Step 7. Check the TRF bit or wait for an SPI serial face for both Master or Slave Mode.
  • Page 37 HT82M75REW/HT82K75REW SPI Configuration Options and Status Control One option is to enable the operation of the WCOL, write collision bit, in the SBCR register. Some control in SPIR register. The SPI_CPOL select the clock polarity of the SCK line . The SPI_MODE select SPI data output mode.
  • Page 38 HT82M75REW/HT82K75REW S P I _ m o d e = 0 S B E N = 1 , C S E N = 0 a n d w r i t e d a t a t o S B D R ( I / O...
  • Page 39 HT82M75REW/HT82K75REW S P I T r a n s f e r W r i t e D a t a i n t o C l e a r W C O L S B D R M a s t e r...
  • Page 40: Configuration Options

    HT82M75REW/HT82K75REW Configuration Options Options PA0~7 Pull-high by bit: Pull-high or non-pull-high PA wake-up by bit, :Wake-up or non-wake-up PB Pull-high by nibble : Pull-high or non-pull-high PC Pull-high by nibble : Pull-high or non-pull-high SPI_WCOL enable/disable (default) Output slew enable 100ns or 200ns TBHP function (enable /disable) DC_DC output option:2.8V,3.0V,3.3V...
  • Page 41 HT82M75REW/HT82K75REW EEPROM Data Memory EEPROM Memory Features · · Device Operations: 1K capacity organized into 128´8 Byte Write Operation · Accessible using two I C lines Current Address Read Operation · Device address: 0´1010000B followed with a Random Address Read Operation...
  • Page 42 HT82M75REW/HT82K75REW EEPROM Data Memory Functional Description · The embedded EEPROM Data Memory is an I2C type Serial clock - SCL The SCL line is the EEPROM serial clock input line device and therefore operates using a two wire serial which is controlled by the host MCU I/O pin. The host bus.
  • Page 43 HT82M75REW/HT82K75REW · Read operations If the comparison of the device address is successful The data EEPROM supports three read operations, then the EEPROM will output a zero as an ACK bit. If namely, current address read, random address read not, the EEPROM will return to a standby state.
  • Page 44: Timing Diagrams

    HT82M75REW/HT82K75REW D e v i c e a d d r e s s D A T A S t o p S D A S t a r t A C K N o A C K Current Read Timing...
  • Page 45 HT82M75REW/HT82K75REW RF Transceiver RF Transceiver Features RF/Analog Circuit Features MAC/Baseband Features · · ISM band 2.400GHz~2.495GHz operation Automatic ACK response and FCS check · · -90dBm/-80dBm sensitivity @ 250k/1M bps 62-byte TX FIFO (Packet error rate under 0.1%) · Dual 64-byte RX FIFOs ·...
  • Page 46 HT82M75REW/HT82K75REW RF Transceiver Power-on and Reset Characteristics consists of TX/RX control and digital signal processing module. Interconnection between the MCU and the RF The RF Transceiver has built-in power-on reset (POR) Transceiver is implemented by internally connecting the circuit which automatically resets all digital registers MCU Master SPI interface to the RF Transceiver Slave when the power is turned on.
  • Page 47 HT82M75REW/HT82K75REW RF Transceiver PHY Block The key features and the block diagram of the PHY layer Under 1M bps turbo mode, user can use the same pro- in RF Transceiver are listed as below. gram settings of MAC and all MAC functions are re- mained the same.
  • Page 48 HT82M75REW/HT82K75REW RF Transceiver Low MAC Block from the recipient device. If the bit is ²1², the recipient The RF Transceiver MAC provides plenty of hard- device shall send an acknowledgement frame back ware-assisted features to relieve the host MCU power after determining that the received frame is valid.
  • Page 49 HT82M75REW/HT82K75REW TXMAC [0], RXMAC automatically switches between RXFIFO0 and RXFIFO1 to store incoming frame whenever a new When the TXFIFO is triggered, the TXMAC gets the packet comes. When the MCU host reads the long ad- data from TXFIFO to generate a 16-bit FCS and sends dress memory 0x300H, the RXMAC will change the flag the packet to the PHY layer of the TX immediately.
  • Page 50 HT82M75REW/HT82K75REW · Auto Acknowledgement Auto-retransmission on TX Side To automatically retransmit a packet when an ACK is The RXMAC supports automatically acknowledgement. not received, SREG0x1B [2] is required to be set to If and only if the packet is successfully received and an ²1².
  • Page 51 HT82M75REW/HT82K75REW RF Transceiver Memory Block · The Memory Block of the RF Transceiver is imple- Short address register (6-bit short addressing mode register, total 64 registers) mented by the SRAM. As the following Memory Block · diagram shown, the RF Transceiver Memory is com-...
  • Page 52 HT82M75REW/HT82K75REW Short Address Registers Legend: r=reserved File Value on Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name 0x00 RXMCR NOACKRSP 0000 0000 0x03 AUINFL AUINF7 AUINF6 AUINF5 AUINF4 AUINF3 AUINF2...
  • Page 53 HT82M75REW/HT82K75REW Long Address Registers Legend: r=reserved File Value on Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name 0x200 RFCTRL0 CHANNEL3 CHANNEL2 CHANNEL1 CHANNEL0 0000 0001 0x201 RFCTRL1 VCORX1 VCORX0 0000 0001...
  • Page 54 HT82M75REW/HT82K75REW FIFOs serve as the temporary data buffers for data The RF Transceiver has four power saving modes that transmission and reception. Each FIFO holds only one will be further described in Power Saving Modes Sec- packet at a time. TXFIFO, the transmission FIFO, is tion.
  • Page 55 HT82M75REW/HT82K75REW DC-DC Converter · POWER_DOWN: All power is shutdown. Registers There are two ways to supply power to the RF Trans- and FIFOs data are not retained, a wake-up input sig- ceiver. One is through the on-chip DC-DC converter and nal can wake up the RF Transceiver.
  • Page 56 HT82M75REW/HT82K75REW ¨ SPI Addressing Format MSB of addressing frame indicates the addressing mode of the packet. The length of address field is 6 or 10 bits for short and long addressing mode respectively. Bit 0 is a one-bit read/write indicator.
  • Page 57 HT82M75REW/HT82K75REW The SPI burst mode is provided for the access of long address memory space on a continuous basis. If SEN does not go high after the 8-bit write data and the SCLK continuously toggles, the followed 8-bit write data is written to the next address field.
  • Page 58 HT82M75REW/HT82K75REW RF Transceiver Application Guide Some typical applications are described in this section to help user gains more understanding of the operation of the RF Transceiver. RF Transceiver Hardware Connection A typical application connection is shown in Application Circuit section. The MCU host serves as a master role, and the RF Transceiver serves as a slave role.
  • Page 59 HT82M75REW/HT82K75REW · Registers associated with Initialization File Value on Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name 0x17 PACON PAONTS3 PAONTS2 PAONTS1 PAONTS0 0000 0010 0x18 TXCON TXONTS3 TXONTS2 TXONTS1...
  • Page 60 HT82M75REW/HT82K75REW RF Transceiver Interrupt Configuration The RF Transceiver issues a hardware interrupt at the internally connected interrupt signal line named INT to the MCU host. There are two related registers that need to be set correctly. All the interrupts are masked (disabled) by default.
  • Page 61 HT82M75REW/HT82K75REW Typical RF Transceiver TX Operation The TXMAC inside the RF Transceiver will automatically generate the preamble, Start-of-Frame Delimiter and the FCS when transmitting. The MCU host must write all other frame fields into TXFIFO for TX operation. To send a packet in TX FIFO, there are several steps to follow: Fill necessary data in TXFIFO.
  • Page 62 HT82M75REW/HT82K75REW RF Transceiver Power Saving Operation Standby, Deep-Sleep and Power-Down Modes are designed for the RF Transceiver. It is only allowed to switch be- tween power saving modes and active mode. The following settings are effective in active mode only.
  • Page 63 HT82M75REW/HT82K75REW RF Transceiver Wake-up Operation After entering into Power Saving Mode, the RF Transceiver could be waked up by the internal register trigger. One and only one method should be used for wake-up operation. · Configure clock recovery time WAKECNT, used to calculate for recovery time of 32MHz clock of the RF Transceiver, should be set in advance. User shall follow the following two steps to configure WAKECNT.
  • Page 64 HT82M75REW/HT82K75REW Primary RF Transceiver TX Operation Users activate the primary TX mode by setting SREG0x0D [2] to 1. After changing the SREG0x0D [2] value, users have to reset the RF and let RF state machine go to primary TX mode correctly. If primary TX mode is enabled, the RF Transceiver will enter power waving mode after ant packet transmits.
  • Page 65 HT82M75REW/HT82K75REW RF Transceiver Short Addressing Registers (SREG0x00~SREG0x3F) 0x00 RXMCR 0x12 ACKTO 0x22 WAKECTL 0x30 RXSR 0x03 AUINFL 0x17 PACON 0x24 TXSR 0x31 ISRSTS 0x04 AUINFH 0x18 TXCON 0x26 GATECLK 0x32 INTMSK 0x05 DADR_0 0x1B TXTRIG 0x2A SOFTRST 0x34 BATRXF ¾...
  • Page 66 HT82M75REW/HT82K75REW · SREG0x06 - DADR_1: Device Address 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name DADR15 DADR14 DADR13 DADR12 DADR11 DADR10 DADR9 DADR8 Type Bit 7~0 DADR [15:8]: 32-bit Address of the RF Transceiver ·...
  • Page 67 HT82M75REW/HT82K75REW · SREG0x12 - ACKTO: Acknowledgement Timeout Period Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ¾ Name MATOP6 MATOP5 MATOP4 MATOP3 MATOP2 MATOP1 MATOP0 Type Reserved: maintain as ²0b0² Bit 7...
  • Page 68 HT82M75REW/HT82K75REW · SREG0x1B - TXTRIG: Transmit FIFO Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ¾ ¾ Name TXRTYN3 TXRTYN2 TXRTYN1 TXRTYN0 TXACKREQ TXTRIG Type Bit 7-4 TXRTYN [3:0]: Maximum TX Retry Times...
  • Page 69 HT82M75REW/HT82K75REW · SREG0x26 - GATECLK: Gated Clock control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ¾ ¾ ¾ ¾ ¾ ¾ Name SPISYNC ENTRM Type Reserved: maintain as ²0b00² Bit 7~6...
  • Page 70 HT82M75REW/HT82K75REW · SREG0x30 - RXSR: RX MAC Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ¾ ¾ ¾ ¾ Name RXFFFULL WRFF1 RXFFOVFL RXCRCERR Type Bit 7 RXFFFULL: RX FIFO Full...
  • Page 71 HT82M75REW/HT82K75REW · SREG0x32 - INTMSK: Interrupt Mask control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ¾ ¾ ¾ ¾ ¾ Name WAKEMSK RXMSK TXNMSK Type Reserved: maintain as ²0b1² Bit 7...
  • Page 72 HT82M75REW/HT82K75REW · SREG0x36 - RFCTL: RF Mode Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ¾ ¾ ¾ ¾ ¾ Name WAKECNT8 WAKECNT7 RFRST Type Reserved: Maintain as ²0b000² Bit 7~5...
  • Page 73 HT82M75REW/HT82K75REW · LREG0x200 - RFCTRL0: RF Control Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ¾ ¾ ¾ ¾ Name CHANNEL 3 CHANNEL 2 CHANNEL 1 CHANNEL 0 Type Bit 7~4 CHANNEL [3:0]: Channel Number.
  • Page 74 HT82M75REW/HT82K75REW · LREG0x203 - RFCTRL3: RF Control Register 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ¾ ¾ ¾ Name TXGB4 TXGB3 TXGB2 TXGB1 TXGB0 Type Bit 7-3 TXGB [4:0]: TX Gain Control in dB. Gain step is monotonic and nonlinear with gain resolution of 0.1 ~ 0.5 dB.
  • Page 75 HT82M75REW/HT82K75REW TX Output Power Register Control LREG0x253 [3:0] LREG0x274 [7:0] LREG0x203 [7:3] TX Output Power 11000 -5.3 dBm 11001 -5.7 dBm 11010 -6.2 dBm 11011 -6.5 dBm C6 for DC-DC OFF 11100 -6.9 dBm 11101 -7.4 dBm 11110 -7.9 dBm 11111 -8.3 dBm...
  • Page 76 HT82M75REW/HT82K75REW · LREG0x206 - RFCTRL6: RF Control Register 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ¾ ¾ ¾ Name TXFBW1 TXFBW0 32MXCO1 32MXCO0 BATEN Type Bit 7~6 TXFBW [1:0]: TX Filter...
  • Page 77 HT82M75REW/HT82K75REW · LREG0x20A - SLPCAL_1: Sleep Clock Calibration 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SLPCAL15 SLPCAL14 SLPCAL13 SLPCAL12 SLPCAL11 SLPCAL10 SLPCAL9 SLPCAL8 Type Bit 7-0 SLPCAL [15:8]: Sleep Clock Calibration Counter bit 15~8 A 20-bit calibration counter which calibrates the sleep clock.
  • Page 78 HT82M75REW/HT82K75REW · LREG0x22F - TESTMODE: Test Mode Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ¾ ¾ ¾ ¾ Name MSPI TESTMODE2 TESTMODE1 TESTMODE0 Type Bit 7 MSPI: Multiple SPI Operation...
  • Page 79 HT82M75REW/HT82K75REW · LREG0x250 - RFCTRL50: RF Control Register 50 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ¾ ¾ ¾ Name DCPOC DCOPC3 DCOPC2 DCOPC1 DCOPC0 Type Reserved: Maintain as ²0b000² Bit 7~5...
  • Page 80 HT82M75REW/HT82K75REW · LREG0x253 - RFCTRL53: RF Control Register 53 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ¾ Name FIFOPS DIGITALPS P32MXE PACEN2 PACTRL2-2 PACTRL2-1 PACTRL2-0 Type Reserved: Maintain as ²0b0² Bit 7...
  • Page 81 HT82M75REW/HT82K75REW · LREG0x254 - RFCTRL54: RF Control Register 54 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name 1MCSEN 1MCSCH6 1MCSCH5 1MCSCH4 1MCSCH3 1MCSCH2 1MCSCH1 1MCSCH0 Type Bit 7 1MCSEN: 1 MHz Channel Spacing Enable 1: Enable.
  • Page 82 HT82M75REW/HT82K75REW · LREG0x259 - RFCTRL59: RF Control Register 59 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ¾ ¾ ¾ ¾ ¾ ¾ ¾ Name PLLOPT3 Type Reserved: Maintain as ²0b0000000² Bit 7~1...
  • Page 83 HT82M75REW/HT82K75REW · LREG0x275 - RFCTRL75: RF Control Register 75 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ¾ ¾ ¾ ¾ Name SCLKOPT3 SCLKOPT2 SCLKOPT1 SCLKOPT0 Type Reserved: Maintain as ²0b0001² Bit 7~4...
  • Page 84 HT82M75REW/HT82K75REW RF Transceiver Power-down and Wake-up The MCU and RF Transceiver are powered down independently of each other. The method of powering down the MCU is covered in the previous MCU section of the datasheet. The RF Transceiver must be powered down before the MCU is powered down.
  • Page 85 HT82M75REW/HT82K75REW · As the RF Transceiver slave SPI timing diagram shows, the SPI data output mode selection SPI_MODE and the clock polarity selection SPI_CPOL of the master SPI should be correctly set to fit the slave SPI protocol requirement. To successfully communicate with the RF Transceiver slave SPI, the SPI_MODE and SPI_CPOL of the MCU master SPI should be set to [1, 1].
  • Page 86 HT82M75REW/HT82K75REW Application Circuits with RF Transceiver 15pF 15pF 47pF VCC_3V 47pF 47pF 10nF 4.7uF 10nF VCC_3V 1.2nH 0.47pF 6.8nH 5.6nH 4.7nH 0.47pF VCC_3V VDD_3V BEAD RF_N VDD_2V2 VDD_RF2 VDD_D GPIO0 10nF 47uF GPIO1 VDD_3V GPIO2 HT82M75REW BAT_IN 47uF 0.1uF 0.1uF...
  • Page 87 HT82M75REW/HT82K75REW VDD_3V VDD_3V VDD_3V 0.1uF 220uF 100K 0.1uF 100uH 0.1uF 47uF HT82K75REW VCC_3V BEAD VDD_3V GPIO2 GND_D 0.1uF GPIO1 GPIO0 VDD_RF2 VDD_D N.C. VCC_3V RF_N VDD_2V2 10nF 0.5pF 5.6nH 6.8nH 1.2nH 0.5pF VCC_3V VCC_3V 0.5pF 1.8pF 4.7uF 6.8nH 0.1uF 10nF...
  • Page 88: Instruction Set

    For easier understanding of the various instruction The standard logical operations such as AND, OR, XOR codes, they have been subdivided into several func- and CPL all have their own instruction within the Holtek tional groupings. microcontroller instruction set. As with the case of most...
  • Page 89 In addition to the above functional instructions, a range of other instructions also exist such as the ²HALT² in- ory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for struction for Power-down operations and instructions to...
  • Page 90 HT82M75REW/HT82K75REW Mnemonic Description Cycles Flag Affected Rotate RRA [m] Rotate Data Memory right with result in ACC None Note RR [m] Rotate Data Memory right None RRCA [m] Rotate Data Memory right through Carry with result in ACC Note RRC [m]...
  • Page 91: Instruction Definition

    HT82M75REW/HT82K75REW Instruction Definition ADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ¬ ACC + [m] + C...
  • Page 92 HT82M75REW/HT82K75REW CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then in- crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address.
  • Page 93 HT82M75REW/HT82K75REW CPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ¬ [m] Operation Affected flag(s) CPLA [m]...
  • Page 94 HT82M75REW/HT82K75REW INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1. [m] ¬ [m] + 1 Operation Affected flag(s) INCA [m] Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu- lator.
  • Page 95 HT82M75REW/HT82K75REW OR A,x Logical OR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR op- eration. The result is stored in the Accumulator. ACC ¬ ACC ²OR² x Operation Affected flag(s)
  • Page 96 HT82M75REW/HT82K75REW RLC [m] Rotate Data Memory left through Carry Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0.
  • Page 97 HT82M75REW/HT82K75REW SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are sub- tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
  • Page 98 HT82M75REW/HT82K75REW SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction.
  • Page 99 HT82M75REW/HT82K75REW SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 « [m].7 ~ [m].4 Operation Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged.
  • Page 100 HT82M75REW/HT82K75REW TABRDC [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
  • Page 101: Package Information

    HT82M75REW/HT82K75REW Package Information SAW Type 40-pin (6mm´6mm for 0.85mm) QFN Outline Dimensions · Dimensions in inch Symbol Min. Nom. Max. 0.031 0.033 0.035 0.000 0.001 0.002 ¾ ¾ 0.008 0.007 0.010 0.012 ¾ ¾ 0.236 ¾ ¾ 0.236 ¾ ¾...
  • Page 102 HT82M75REW/HT82K75REW 64-pin LQFP (7mm´7mm) Outline Dimensions Dimensions in mm Symbol Min. Nom. Max. ¾ 8.90 9.10 ¾ 6.90 7.10 ¾ 8.90 9.10 ¾ 6.90 7.10 ¾ ¾ 0.40 ¾ 0.13 0.23 ¾ 1.35 1.45 ¾ ¾ 1.60 ¾ 0.05 0.15 ¾...
  • Page 103 Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as- sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used...

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