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AsahiKASEI AK4493 Manual

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The AK4493 is a new generation Premium 32-bit 2ch DAC with VELVET SOUND
achieving industry's leading level low distortion characteristics. The newly adopted OSR-Doubler
technology establishes wide signal band, low power consumption and low distortion characteristics.
Moreover, the AK4493 has six types of 32-bit digital filters, realizing simple and flexible sound tuning in a
wide range of applications. The AK4493 accepts up to 768kHz PCM data and 22.4MHz DSD data, ideal
for high-resolution audio source playback that is becoming widespread in network audio, USB-DAC, etc.
Application: AV Receivers, CD/SACD Players, Network Audios, USB DACs, USB Headphones, Sound
Plates/Bars, Measurement Equipment, Control Systems, IC-Recorder, Bluetooth
Headphone, HD Audio/Voice Conference Systems.
 THD+N: -113dB
 DR, S/N: 123dB (2Vrms), 125dB (Large Amplitude Mode), 126dB (Mono Mode)
 256 Times Over Sampling
 Sampling Rate: 8kHz  768kHz
 32-bit 8x Digital Filter
- Short Delay Sharp Roll-off, GD = 6.0/fs,
- Short Delay Slow Roll-off, GD = 5.0/fs
- Sharp Roll-off
- Slow Roll-off
- Low Dispersion Short Delay Filter
- Super Slow Roll-off
 High Tolerance to Clock Jitter
 Low Distortion/ Low Noise High Performance Differential Amplifier Output
 Large Amplitude Output Mode
 DSD64, DSD128, DSD256, DSD512 Input Support
- Filter1 (fc = 39kHz, DSD64 mode), Filter2 (fc = 76kHz, DSD64 mode)
 Digital De-emphasis for 32, 44.1 and 48kHz sampling
 Soft Mute
 Digital Attenuator (255 levels and 0.5dB step + mute)
 Mono Mode
 External Digital Filter Interface
 Audio I/F Format: 24/32 bit MSB justified, 16/20/24/32 bit LSB justified, I
 Master Clock
8kHz ~ 32kHz: 256fs or 384fs or 512fs or 768fs or 1152fs
8kHz ~ 54kHz: 256fs or 384fs or 512fs or 768fs
8kHz ~ 108kHz: 256fs or 384fs
108kHz ~ 216kHz: 128fs or 192fs
 3-wire, I
2
C-bus Register Control Interface, or Pin Control
 Power Supply:
TVDD = AVDD = 3.0  3.6V (by internal LDO), VDDL/R = 4.75 ~ 5.25V
TVDD = AVDD = DVDD  3.6V (by external supply), DVDD = 1.7V  1.98V
VDDL/R = 4.75 ~ 5.25V
 Operational Temperature: -40 ~ 85 °C
017012230-E-00
Quality Oriented 32-Bit 2ch DAC
1. General Description

2. Features

~ 384kHz: 32fs or 48fs or 64fs or 96fs
~ 768kHz: 16fs or 32fs or 48fs or 64fs
- 1 -
[AK4493]
AK4493
TM
technology,
2
S, DSD, TDM
2017/12

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Summary of Contents for AsahiKASEI AK4493

  • Page 1: Table Of Contents 1. General Description

    Moreover, the AK4493 has six types of 32-bit digital filters, realizing simple and flexible sound tuning in a wide range of applications. The AK4493 accepts up to 768kHz PCM data and 22.4MHz DSD data, ideal for high-resolution audio source playback that is becoming widespread in network audio, USB-DAC, etc.
  • Page 2 [AK4493]  Digital Input Level: CMOS  Package: 48-pin LQFP 017012230-E-00 2017/12 - 2 -...

  • Page 3: Table Of Contents

    [AK4493] 3. Table of Contents General Description ........................1 Features ............................1 Table of Contents ..........................3 Block Diagram ..........................5 Pin Configurations and Functions ....................6 ■ Pin Configurations ..........................6 ■ Pin Functions ............................. 7 ■ Handling of Unused Pin ........................9 Absolute Maximum Ratings ......................
  • Page 4 [AK4493] Ordering Guide ........................... 103 ■ Ordering Guide ..........................103 Revision History .......................... 103 IMPORTANT NOTICE ..........................104 017012230-E-00 2017/12 - 4 -...

  • Page 5: Block Diagram

    [AK4493] 4. Block Diagram LDOE TVDD DVDD DVSS AVDD AVSS VSSL VDDL De-emphasis BICK/DCLK/BCK & AOUTLP Data SDATA/DSDL/DINL Interpolator Interface AOUTLN LRCK/DSDR/DINR VCML Normal path VREFHL  DSD Data DSDD bit “0” DATT Bias VREFLL Interface Soft Mute Modulator Vref &...

  • Page 6: Pin Configurations And Functions

    [AK4493] 5. Pin Configurations and Functions ■ Pin Configurations VCMR VCML VREFLR VREFLL VREFLR VREFLL AK4493 VREFHR VREFHL VREFHR VREFHL TESTE OUTRP Top View ACKS/CAD1 AVDD LDOE AVSS DEM0 MCLK DVSS INV/I2C TVDD Figure 2. Pin Layout 017012230-E-00 2017/12 - 6 -...

  • Page 7: Pin Functions

    (LDOE pin = “L”) 1.8V Power Input Pin Power-Down Mode Pin When at “L”, the AK4493 is in power-down mode and is held in reset. The AK4493 must always be reset upon power-up. BICK Audio Serial Data Clock Pin in PCM Mode...
  • Page 8 (LDOE pin = “H”) TVDD = 3.0  3.6V, (LDOE pin = “L”) TVDD = DVDD  3.6V Note 1. All input pins except internal pull-up/down pins must not be left floating. Note 2. The AK4493 must be reset by the PDN pin when changing control mode (Pin Control ⇔ Register Control) by the PSN pin.

  • Page 9: Handling Of Unused Pin

    [AK4493] ■ Handling of Unused Pin Unused I/O pins must be connected appropriately. (1) Pin Control Mode (PCM mode only) Classification Pin Name Status AOUTLP, AOUTLN Open Analog AOUTRP, AOUTRN Open Connect to DVSS Digital TESTE or Open (2) Register Control Mode 1.

  • Page 10: Absolute Maximum Ratings

    [AK4493] 5. Pull-up, Pull-down Pin List Classification Pin Name Internal connection pull-up pin (typ = 100kΩ) TVSS pull-down pin(typ = 100kΩ) DZFL, DZFR, TESTE DVSS 6. Absolute Maximum Ratings (AVSS = DVSS = VSSL = VSSR = VREFLL = VREFLR = 0V;...

  • Page 11: Recommended Operating Conditions

    [AK4493] 7. Recommended Operating Conditions (AVSS = DVSS = VSSL = VSSR = VREFLL = VREFLR = 0V; Note Parameter Symbol Min. Typ. Max. Unit ■ LDOE pin = “L” Digital I/O TVDD DVDD Clock Interface AVDD DVDD Digital Core DVDD 1.98...

  • Page 12: Electrical Characteristics

    [AK4493] 8. Electrical Characteristics ■ Analog Characteristics (Ta = 25C; LDOE pin = “L”, AVDD = TVDD = 3.3V, DVDD = 1.8V; AVSS = DVSS = VSSL/R = 0V; VREFHL/R = VDDL/R = 5.0V, VREFLL/R = 0V; Input data = 24bit; BICK = 64fs; Signal Frequency= 1kHz;...
  • Page 13 [AK4493] (Ta = 25C; AVDD = TVDD = 3.3V, DVDD = 1.8V (LDOE pin = “L”), AVSS = DVSS = VSSL/R = 0V; VREFHL/R = VDDL/R = 5.0V, VREFLL/R = 0V; Input data = 24bit; BICK = 64fs; Signal Frequency = 1kHz;...

  • Page 14: Dsd Mode

    [AK4493] ■ DSD Mode (Ta = 25C; AVDD = TVDD = 3.3V, DVDD = 1.8V (LDOE pin = “L”), AVSS = DVSS = VSSL/R = 0V; VREFHL/R = VDDL/R = 5.0V, VREFLL/R = 0V; Signal Frequency = 1kHz; Measurement bandwidth = 81);...

  • Page 15: Sharp Roll-Off Filter Characteristics

    [AK4493] ■ Sharp Roll-Off Filter Characteristics Sharp Roll-Off Filter Characteristics (fs = 44.1kHz) (Ta = -40 ~ 85C; VDDL/R = 4.75  5.25V, AVDD = TVDD = 1.7  3.6V, DVDD = 1.7~ 1.98V; Normal Speed Mode; DEM = OFF; SD bit = “0” or SD pin = “L”, SLOW bit = “0” or SLOW pin = “L”, SSLOW bit = “0”...
  • Page 16 [AK4493] Note 27. The passband and stopband frequencies scale with fs. For example, PB = 0.4535×fs (@0.01dB), SB = 0.546×fs. Note 28. This value is the gain amplitude of first step interpolator which is 4 times oversampling filter in pass band width.

  • Page 17: Slow Roll-Off Filter Characteristics

    [AK4493] ■ Slow Roll-Off Filter Characteristics Slow Roll-Off Filter Characteristics (fs = 44.1kHz) (Ta = -40~85C; VDDL/R = 4.755.25V, AVDD = TVDD = 1.7~3.6V, DVDD = 1.7~1.98V; Normal Speed Mode; DEM = OFF; SD bit = “0” or SD pin = “L”, SLOW bit = “1” or SLOW pin = “H”, SSLOW bit = “0” or SSLOW pin = “L”)
  • Page 18 [AK4493] Figure 5. Slow Roll-off Filter Frequency Response Figure 6. Slow Roll-off Filter Passband Ripple 017012230-E-00 2017/12 - 18 -...

  • Page 19: Short Delay Sharp Roll-Off Filter Characteristics

    [AK4493] ■ Short Delay Sharp Roll-Off Filter Characteristics Short Delay Sharp Roll-Off Filter Characteristics (fs = 44.1kHz) (Ta = -40 ~ 85C; VDDL/R = 4.75  5.25V, AVDD = TVDD = 1.7  3.6V, DVDD = 1.7 ~ 1.98V; Normal Speed Mode; DEM = OFF; SD bit = “1” or SD pin = “H”, SLOW bit = “0” or SLOW pin = “L”, SSLOW bit = “0”...
  • Page 20 [AK4493] Figure 7. Short Delay Sharp Roll-off Filter Frequency Response Figure 8. Short Delay Sharp Roll-off Filter Passband Ripple 017012230-E-00 2017/12 - 20 -...

  • Page 21: Short Delay Slow Roll-Off Filter Characteristics

    [AK4493] ■ Short Delay Slow Roll-Off Filter Characteristics Short Delay Slow Roll-Off Filter Characteristics (fs = 44.1kHz) (Ta = -40 ~ 85C; VDDL/R = 4.75  5.25V, AVDD = TVDD = 1.7  3.6V, DVDD = 1.7 ~ 1.98V; Normal Speed Mode; DEM = OFF; SD bit = “1” or SD pin = “H”, SLOW bit = “1” or SLOW pin = “H”, SSLOW bit = “0”...
  • Page 22 [AK4493] Figure 9. Short Delay Slow Roll-off Filter Frequency Response Figure 10. Short Delay Slow Roll-off Filter Passband Ripple 017012230-E-00 2017/12 - 22 -...

  • Page 23: Low Dispersion Short Delay Filter Characteristics

    [AK4493] ■ Low Dispersion Short Delay Filter Characteristics Low Dispersion Short Delay Filter Characteristics (fs = 44.1kHz) (Ta = -40 ~ 85C; VDDL/R = 4.75  5.25V, AVDD = TVDD = 1.7  3.6V, DVDD = 1.7 ~ 1.98V; Normal Speed Mode; DEM = OFF; SD bit = “1” or SD pin = “H”, SLOW bit = “X” or SLOW pin = “X”, SSLOW bit = “1”...
  • Page 24 [AK4493] Figure 11. Low Dispersion Short Delay Filter Frequency Response Figure 12. Low Dispersion Short Delay Filter Passband Ripple 017012230-E-00 2017/12 - 24 -...

  • Page 25: Dsd Filter Characteristics

    [AK4493] ■ DSD Filter Characteristics (Ta = -40 ~ 85C; VDDL/R = 4.75  5.25V, AVDD = TVDD = 1.7  3.6V, DVDD = 1.7  1.98V; fs = 44.1kHz; DP bit = “1”, DSDF bit = “0”, DSDSEL[1:0] bits = “00”...

  • Page 26: Switching Characteristics

    1/512fs nsec Low time tLRL 1/512fs nsec Note 37. The MCLK frequency must be changed while the AK4493 is in reset state by setting the PDN pin = “L” or RSTN bit = “0”. 017012230-E-00 2017/12 - 26 -...
  • Page 27 [AK4493] Parameter Symbol Min. Typ. Max. Unit PCM Audio Interface Timing Normal Mode (TDM[1:0] bits = “00”) BICK Period Normal Speed Mode tBCK 1/256fsn nsec Double Speed Mode tBCK 1/128fsd nsec Quad Speed Mode tBCK 1/64fsq nsec Oct speed mode...
  • Page 28 DCKB bit = “1”. If the audio data format is in phase modulation mode, “tDDD” is defined from DCLK edge “↓” or “↑” until DSDL/R edge regardless of DCKB bit setting. Note 40. The AK4493 does not support Phase Modulation Mode in DSD512 Mode. 017012230-E-00...
  • Page 29 Note 41. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 42. The AK4493 can be reset by bringing the PDN pin “H” upon power-up. Note 43. I C -bus is a trademark of NXP B.V.

  • Page 30: Timing Diagram

    [AK4493] ■ Timing Diagram 1/fCLK MCLK tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs LRCK tLRH tLRL tBCK BICK tBCKH tBCKL tWCK tWCKH tWCKL Figure 13. Clock Timing 017012230-E-00 2017/12 - 30 -...
  • Page 31 [AK4493] LRCK tBLR tLRB BICK tSDH tSDS SDATA Figure 14. Audio Interface Timing (PCM Mode) DINL DINR Figure 15. Audio Interface Timing (External Digital Filter I/F Mode) 017012230-E-00 2017/12 - 31 -...
  • Page 32 [AK4493] tDCK tDCKL tDCKH DCLK tDDD DSDL DSDR tDDD DSDL DSDR DSD Audio Interface Timing (DSD64, DSD128, DSD256 Mode) tDCK tDCKL tDCKH DCLK tDDS tDDH DSDL DSDR DSD Audio Interface Timing (DSD512 Mode) Figure 16. Audio Interface Timing (DSD Normal Mode, DCKB bit = “0”)
  • Page 33 [AK4493] tCCK tCSS tCCKL tCCKH CCLK tCDS tCDH CDTI Figure 18. WRITE Command Input Timing tCSW tCSH CCLK CDTI Figure 19. WRITE Data Input Timing 017012230-E-00 2017/12 - 33 -...
  • Page 34 [AK4493] tBUF tLOW tHIGH tHD:STA tHD:DAT tSU:DAT tSU:STA tSU:STO Stop Start Start Stop Figure 20. I C Bus Mode Timing tAPD tRPD Figure 21. Power Down & Reset Timing 017012230-E-00 2017/12 - 34 -...

  • Page 35: Functional Descriptions

    Each function of the AK4493 is controlled by pins (Pin Control Mode) or registers (Register Control Mode) (Table 1). Select the control mode by setting the PSN pin. The AK4493 must be powered down by the PDN pin when changing the PSN pin setting. There is a possibility of malfunction if the device is not powered down when changing the control mode since the previous setting is not reinitialized.
  • Page 36 [AK4493] Table 3. Function List of PCM/EXDF/DSD Mode in Register Control Mode Function Default Address PCM EXDF DSD EXDF PCM mode PCM/DSD /EXDF Mode Select DSD512 DCKS System Clock Setting in DSD Mode System Clock Setting in EXDF 16fs Mode...

  • Page 37: D/A Conversion Mode (Pcm Mode, Dsd Mode, Exdf Mode)

    D/A Conversion Mode (PCM Mode, DSD Mode, EXDF Mode) The AK4493 is able to convert either PCM or DSD data to an analog signal, and an external digital filter I/F can also be selected. In PCM mode, PCM data can be input from the BICK, LRCK and SDATA pins. In DSD mode, DSD data can be input from the DCLK, DSDL and DSDR pins.

  • Page 38: D/A Conversion Mode Switching Timing

    [AK4493] ■ D/A Conversion Mode Switching Timing Figure 22 Figure 23 show switching timing of PCM/EXDF and DSD modes. To prevent noise caused by excessive input, DSD signal should be input 4/fs after setting RSTN bit = “0” until the device is completely reset internally when the conversion mode is changed to DSD mode from PCM/EXDF mode.

  • Page 39: System Clock

    Normal Speed Mode in Pin Control Mode (PSN pin = “H”), and it is set by DFS[2:0] bits in Register Control Mode (PSN pin = “L”). In Register Control Mode, the AK4493 is in Manual Setting Mode when power-down is released (PDN pin = “L”...
  • Page 40 Auto Setting Mode is a function that enables to playback 44.1kHz, 96kHz and 192kHz audio data without setting registers if an MCLK about 22.5792MHz is input to the AK4493. The AK4493 can operate with an MCLK about 11.2896MHz, however the characteristics will degrade since it is not an intended speed.
  • Page 41 MCLK frequency corresponding to each sampling speed that should be provided externally (Table 13). The AK4493 is set to Manual Setting Mode at power-up (PDN pin = “L”→“H”). When DFS2-0 Table bits are changed, the AK4493 should be reset by RSTN bit.
  • Page 42 [AK4493] 2-2. Auto Setting Mode (AFSD bit = “0”, ACKS bit = “1”) MCLK frequency and the sampling speed are detected automatically (Table 14) and DFS[2:0] bits are ignored. The MCLK frequency corresponding to each sampling speed should be provided externally...
  • Page 43 [2] DSD Mode (Register Control Mode only) The AK4493 has a DSD playback function. The external clocks that are required in DSD mode are MCLK and DCLK. MCLK should be synchronized with DCLK but the phase is not critical. The frequency of...
  • Page 44 AK4493 starts operation by inputting MCLK again. In this case, register settings are not initialized. When the reset is released (PDN pin = “L” → “H”), the AK4493 is in power-down state until MCLK, BCK and WCK are input.

  • Page 45: Audio Interface Format

    [AK4493] ■ Audio Interface Format [1] PCM Mode (1) Input Data Format Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported and selected by the DIF2-0 pins (Pin Control Mode) or DIF[2:0] bits (Register Control Mode) as shown in Table 22.
  • Page 46 [AK4493] Table 22. Audio Interface Format (PCM mode) TDM1 TDM0 Mode DIF2 DIF1 DIF0 SDATA Format BICK Figure 32fs 16-bit LSB justified Figure 25 40fs 20-bit LSB justified Figure 26 48fs 24-bit MSB justified Figure 27 16-bit I compatible 32fs...
  • Page 47 [AK4493] LRCK BICK (32fs) SDATA BICK (64fs) SDATA Don’t care 15 14 Don’t care 15 14 15:MSB, 0:LSB Lch Data Rch Data Figure 25. Mode 0 Timing LRCK BICK (64fs) SDATA Don’t care Don’t care Mode 1 19:MSB, 0:LSB SDATA Don’t care...
  • Page 48 [AK4493] LRCK BICK (64fs) SDATA Don’t care Don’t care 23:MSB, 0:LSB Lch Data Rch Data Figure 28. Mode 3 Timing LRCK BICK (128fs) SDATA BICK (64fs) SDATA 20 19 18 31 30 19 18 Lch Data Rch Data 31: MSB, 0:LSB Figure 29.
  • Page 49 [AK4493] LRCK BICK (128fs) SDATA 13 12 11 12 11 BICK (64fs) SDATA 21 20 19 20 19 Lch Data Rch Data 31: MSB, 0:LSB Figure 31. Mode 7 Timing 128 BICK LRCK BICK (128fs) SDATA Mode8 SDATA Mode11/12 32 BICK...
  • Page 50 [AK4493] 128 BICK LRCK BICK (128fs) SDATA 32 BICK 32 BICK 32 BICK 32 BICK Figure 34. Mode 10 Timing 256 BICK LRCK BICK (256fs) SDATA Mode14 SDATA 31 30 31 30 Mode17/18 32 BICK 32 BICK 32 BICK 32 BICK...
  • Page 51 [AK4493] 512 BICK LRCK BICK (512fs) SDATA Mode20 SDATA Mode23/24 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 38.
  • Page 52 [AK4493] (2) Data Slot Selection Function Data slot of 1cycle LRCK for each audio data format is defined as Figure 41 ~ Figure 44. DAC output data can be selected by SDS[2:0] bits (Register Control Mode only), as shown in...
  • Page 53 The frequency of DCLK is selected among 64fs, 128fs, 256fs and 512fs by DSDSEL[1:0] bits. Polarity of DCLK is possible to invert by DCKB bit. The AK4493 does not support phase modulation when DCLK is 512fs (DSDSEL[1:0] bits = “11”).
  • Page 54 [AK4493] [3] External Digital Filter Mode (EXDF mode; Register Control Mode only) The audio data is input by MCLK, BCK and WCK from the DINL and DINR pins. Three formats are available (Table 24) by DIF2-0 bits setting. The data is latched on the rising edge of BCK. The BCK and MCLK clocks must not burst.

  • Page 55: Digital Filter

    AK4493 for sound color selection of music playback. In PCM mode, the digital filter can be selected by the SD, SLOW and SSLOW pins if the AK4493 is in Pin Control Mode, and it can be selected by the SD, SLOW and SSLOW bits in Register Control Mode (Table 25).

  • Page 56: Output Volume (Pcm, Dsd And Exdf Modes; Register Control Mode Only)

    Output Volume (PCM, DSD and EXDF Modes; Register Control Mode only) The AK4493 includes channel independent digital output volumes (ATTL/R) with 256 levels at 0.5dB step including MUTE. When changing output levels, it is executed in soft transition, thus no switching noise occurs during these transitions.

  • Page 57: Gain Adjustment Function (Pcm, Dsd And Exdf Modes; Register Control Mode Only)

    [AK4493] ■ Gain Adjustment Function (PCM, DSD and EXDF Modes; Register Control Mode only) The AK4493 has the gain adjustment function. The analog output amplitude can be adjusted by GC[2:0] bits. Table 31. Output Level between Set Values of GC[2:0]bit...
  • Page 58 [AK4493] Figure 47. Zero Detection Monitor Node Table 32. Zero Detect Selection DZFE DZFB RSTN Data DZF-pin (default) not zero zero detect not zero zero detect (*: Do not care) The DZFL/R pin also has DSD full-scale detection output function. DSD full-scale detection signal (DMR, DML) is output from the DZFL/R pin when DDMOE bit = “1”.

  • Page 59: Lr Channel Output Signal Select, Phase Inversion Function (Pcm, Dsd And Exdf Modes)

    Rch In Lch In Invert Rch In Invert * With the INV function, it is assumed that the AK4493 is connected to the AK4205 without crossing the signal lines. ■ Sound Quality Adjustment Function (PCM, DSD, EXDF; Register Control Mode only) Sound quality of the AK4493 can be controlled by setting SC[2:0] bits.

  • Page 60: Dsd Signal Full-Scale (Fs) Detection

    AK4493 is in full-scale state. When DSDD bit = “0” (Normal Path), the output data of DSD filter is changed to Zero data and the data is soft muted by DATT block if the AK4493 is in full-scale state. Mute transition time is set by ATS[1:0] bits from 255/2fs to 4080/2fs (fs = 30~48kHz in DSD mode).
  • Page 61 [AK4493] Table 38. DSD Signal Full-scale Detection Time Setting Detection Time DDMT1 DDMT0 Register Delay 256 DCLK Cycles (default) 264 DCLK Cycles 512 DCLK Cycles 520 DCLK Cycles 1024 DCLK Cycles 1032 DCLK Cycles 128 DCLK Cycles 136 DCLK Cycles Table 39.
  • Page 62 “1” if the input data is full-scale for a period set by DDMT[1:0] bits after releasing internal reset. (2) Analog output is forced to zero (VCML/R level) when the AK4493 detects full-scale data. (3) Analog output delays for the period set by DDMT[1:0] bits + 8DCLK cycles when setting DDM bit = “1”.

  • Page 63: Automatic Mode Switching Function (Pcm/Exdf ⇔ Dsd Mode; Register Control Mode Only)

    BCK/DCLK pin (#3) has rising edges more than 256 times during one rising edge cycle of the input clock of the WCK pin (#6). The AK4493 detects EXDF mode if an input clock to the BCK/DCLK pin (#3) has rising edge less than or equal to 256 times for two rising edge cycles of the input clock of the WCK pin (#6) continuously.
  • Page 64 [AK4493] Table 40. Time Until Mode Detection when Input Data Becomes Zero ADPT1 ADPT0 Wait Time for Zero Data (default) 8192/fs 4096/fs 2048/fs 1024/fs Note: fs=30~48kHz in DSD mode Table 41. Mode Detection Conditions when EXDF bit = “0” #4 LRCK/DSDR Input Signal...
  • Page 65 In this case, delay time depends on DDMT[1:0] bits setting. (7) If BICK input is stopped in PCM mode, the AK4493 stays in PCM mode and continues operation. Figure 51. Changing to DSD Mode after Power-up In PCM Mode (EXDF bit = “0”)
  • Page 66 = “0”. (7) If DCLK input is stopped in DSD mode, the AK4493 stays in DSD mode and continues operation. (8) Upon power up the AK4493, the AK4493 operates in PCM mode if DCLK is input and DSDR is not input.
  • Page 67 (1) The transition time to mute completely by setting SMUTE bit = “1” is set by ATS[1:0] bits. (2) The AK4493 starts mode detection when input data of both channels are continuously zero for the period set by ADPT[1:0] bits, and it finishes mode detection when a data that is not zero is input.
  • Page 68 In this case, delay time depends on DDMT[1:0] bits setting. (8) If BICK input is stopped in EXDF mode, the AK4493 stays in EXDF mode and continues operation. (9) WCK input should be “L” when using DSD mode since DSD mode detection is performed by monitoring presence or absence of the WCK input clock.
  • Page 69 (8) If DCLK input is stopped in DSD mode, the AK4493 stays in DSD mode and continues operation. (9) If DSDR input is stopped in DSD mode, the AK4493 stays in DSD mode and continues operation. In this case, full-scale data is input to the AK4493. Excessive signal output can be avoided by setting DDM bit = “1”...
  • Page 70 (1) The transition time to mute completely by setting SMUTE bit = “1” is set by ATS[1:0] bits. (2) The AK4493 starts mode detection when input data of both channels are continuously zero for the period set by ADPT[1:0] bits, and it finishes mode detection when a data that is not zero is input.

  • Page 71: Soft Mute Operation (Pcm, Dsd, Exdf)

    [AK4493] ■ Soft Mute Operation (PCM, DSD, EXDF) The soft mute operation is performed at digital domain. When setting the SMUTE pin to “H” or SMUTE bit to “1”, the output signal is attenuated by  during ATT_DATA  ATT transition time from the current ATT level.

  • Page 72: Ldo

    In this case, the analog signal output and the PDA pin becomes Hi-z state (In I C mode, ACK is not output). The AK4493 must be reset by setting the PDN pin = “L” → “H” to recover from the error detection status.

  • Page 73: Power Up/Down Function

    ■ Power Up/Down Function The AK4493 is powered down when the PDN pin is “L”. In power-down state, all circuits stop operation and initialized, and the analog output becomes floating (Hi-z) state. The PDN pin must held “L” for more than 150ns for a certain reset after all power supplies are on.
  • Page 74 [AK4493] The timing example when not using the internal LDO (LDOE pin = “L”) is shown in Figure When the LDOE pin = “L”, TVDD must be powered up before or at the same time of the DVDD. Power (TVDD)
  • Page 75 MCLK and DCLK for DSD mode, MCLK, BCK and WCK for EXDF mode) and the clock divider is powered up about after 4/fs. In this time, the analog output pins output analog common voltages (VCML, VCMR). Then the AK4493 transitions to normal operation by setting RSTN bit = “1”. Power...
  • Page 76 [AK4493] Figure 60. Power-down/up Sequence Example (Register Control Mode, LDOE pin = “H”) The system timing example of power up/down when not using LDO (LODE pin = “L”) is shown in Figure 61. When the LDOE pin = “L”, TVDD must be powered up before or at the same time of DVDD.

  • Page 77: Power-Off/Reset Function

    (min.) during operation (PDN pin = “H”). In this case, the analog output goes floating state (Hi-Z). The AK4493 returns to normal operation if PW bit and RSTN bit are “1” after starting to supply MCLK again. The zero detect function is disabled when MCLK is stopped.
  • Page 78 (3) Click noise occurs on an edge of PW bit. This noise is output even if “0” data is input. (4) The zero detect function is enable when the AK4493 is power off (PW bit = “0”). This figure shows the seuqnece when DZFE bit = “1”, DZFB bit = “0”...
  • Page 79 [AK4493] [3] Reset by RSTN bit Digital circuits except control registers and clock divider are reset by setting RSTN bit to “0”. In this case, control register settings are held, the analog output becomes VCML/R voltage and the DZFL/R pin outputs “H”.

  • Page 80: Synchronize Function (Pcm, Exdf)

    Synchronize Function (PCM, EXDF) The AK4493 has a function that resets the internal counter to keep the timing of falling edge of the internal clock CLK1 and the external clock edge in a certain range. With this synchronize function, group delays between each device can be kept within 4/256fs when using multiple AK4493’s.
  • Page 81 [AK4493] If RSTN bit is set to “0”, the output signal of the DZFL/R pin becomes “H”. Then, the DAC is reset after 3~ 4/fs and the analog output becomes the same voltage as VCML/R. The synchronize function becomes valid when both of the DZFL and the DZFR pins output “H”.

  • Page 82: Register Control Interface

    When the state of the PSN pin is changed, the AK4493 should be powered down by the PDN pin. Otherwise, malfunctions may occur since previous settings are not initialized. The register control interface is enabled by setting the PSN pin = “L”.
  • Page 83 “0” indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4493 and the format is MSB first. The most significant three bits are fixed as “000”...
  • Page 84 [AK4493] (2)-2. READ Operation Set the R/W bit = “1” for the READ operation of the AK4493. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
  • Page 85 [AK4493] start condition stop condition Figure 74. Start Condition and Stop Condition DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER clock pulse for acknowledgement START CONDITION Figure 75. Acknowledge (I C Bus) data line change stable;...

  • Page 86: Register Map

    • When the PSN pin status is changed, the AK4493 should be reset by the PDN pin. (*) The AK4493 is a register compatible device with the AK4490, the AK4495S and the AK4497.
  • Page 87 [AK4493] AK4490 Register Map (Reference) Register Addr Name Control 1 ACKS EXDF DIF2 DIF1 DIF0 RSTN Control 2 DZFE DZFM DFS1 DFS0 DEM1 DEM0 SMUTE Control 3 DCKS DCKB MONO DZFB SELLR SLOW Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3...

  • Page 88: Register Definitions

    [AK4493] ■ Register Definitions Addr Register Name 00H Control 1 ACKS EXDF DIF2 DIF1 DIF0 RSTN Default RSTN: Internal Timing Reset 0: Reset. All registers are not initialized. (default) 1: Normal Operation DIF[2:0]: Audio Data Interface Modes (Table Initial value is “110” (Mode6: 32bit MSB justified).
  • Page 89 [AK4493] Addr Register Name 01H Control 2 DZFE DZFM DFS1 DFS0 DEM1 DEM0 SMUTE Default SMUTE: Soft Mute Enable 0: Normal Operation (default) 1: DAC outputs soft-muted. DEM[1:0]: De-emphasis Filter Control (Table Initial value is “01” (OFF). DFS[1:0]: Sampling Speed Control.
  • Page 90 It is invalid when ADPE bit = “0” and readouts “0” when read. 0: PCM Mode/EXDF Mode 1: DSD Mode DSD/PCM Mode Select 0: PCM Mode (default) 1: DSD Mode When DP bit is changed, the AK4493 should be reset by RSTN bit. 017012230-E-00 2017/12 - 90 -...
  • Page 91 [AK4493] Addr Register Name 03H Lch ATT ATTL7 ATTL6 ATTL5 ATTL4 ATTL3 ATTL2 ATTL1 ATTL0 04H Rch ATT ATTR7 ATTR6 ATTR5 ATTR4 ATTR3 ATTR2 ATTR1 ATTR0 Default ATTL[7:0]: Attenuation Level ATTR[7:0]: Attenuation Level 255 levels 0.5dB step + mute Data...
  • Page 92 DMR/DML: This register outputs detection flag when a full-scale signal is detected at DSDR/L channel. DDM: DSD Data Mute The AK4493 has an internal mute function that mutes the output when DSD input data becomes all “1” or all “0” for 2048 samples (1/fs) continuously. DDM bit controls this function.
  • Page 93 [AK4493] Addr Register Name 07H Control 5 SYNCE Default SYNCE: SYNC Mode Enable 0: SYNC Mode Disable 1: SYNC Mode Enable (default) GC[2:0]: PCM, DSD mode Gain Control (Table Addr Register Name 08H Sound Control Default SC[2:0]: Sound Control. (Table...
  • Page 94 [AK4493] Addr Register Name 0BH Control 7 ATS1 ATS0 SDS0 TEST Default TEST: “0” value must be written to this bit. Otherwise malfunctions may occur. SDS[2:0]: Output Data Slot Selection for Each Channel 0: Normal 1: Output Data of Other Slot...
  • Page 95 [AK4493] Addr Register Name 15H Control 8 ADPE ADPT1 ADPT0 Default ADPT[1:0]: Time until PCM/DSD mode detection when input data becomes zero (PCM/EXDF⇔DSD modes) (Table 40). ADPE: Automatic Mode Switching Function Enable Bit for PCM/EXDF and DSD Modes 0: Disable (default)

  • Page 96: Recommended External Circuits

    [AK4493] 10. Recommended External Circuits 10.1 pin control mode, LDO disable. Reference Voltage 5.0V Analog 1.8V Reference Voltage 0V Analog 5.0V Digital 1.8V Digital 1.8V µ µ µ µ µ µ µ µ µ DVDD AOUTLP Lch Out Mute AOUTLN BICK µ...
  • Page 97 [AK4493] 10.2 pin control mode, LDO enable. Reference Voltage 5.0V Analog 3.3V Reference Voltage 0V Analog 5.0V Digital 3.3V µ µ µ µ µ µ µ µ µ DVDD AOUTLP Lch Out Mute AOUTLN BICK µ µ VDDL SDATA VDDL...
  • Page 98 AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane. Decoupling capacitors for high frequency should be placed as near as possible to the AK4493. 2. Reference Voltage The differential voltage between VREFHL and VREFLL, and VREFHR and VREFLR set the full-scale of the analog output range.
  • Page 99 [AK4493] AK4493 2.37k AOUTLN/RN 750p 9.5n +Vop Analog 20.5 AOUTLP/RP OPA1611 -Vop 5.1n Figure 79. External LPF Circuit Example 1 (fc = 104kHz(typ), Q=0.690(typ)) Table 48. Frequency Response of External LPF Circuit Example 1 Gain(1kHz,Typ) +8.75 dB Frequency 20kHz -0.02 dB...
  • Page 100 [AK4493] 5.6n µ AK4493 µ OPA1612 µ AOUTLN/RN µ µ 1.65k 5.6n µ µ µ OPA1612 LME49710 AOUTLP/RP µ µ 1.65k Figure 81. External LPF Circuit Example 3 (fc = 178kHz(typ), Q=0.67(typ)) Table 50. Frequency Response of External LPF Circuit Example 3 Gain(1kHz,Typ) +9.54 dB...

  • Page 101: Package

    [AK4493] 11. Package ■ Outline Dimensions (48-pin LQFP) 9.00 7.00 0 ～ ゜ 7゜ 0.50 0.22±0.05 0.10 1.00 0.10 S 0.60±0.15 ■ Material & Terminal Finish Package Molding Compound: Epoxy, Halogen (Br and Cl) free Lead Frame Material: EFTEC-64T Terminal Surface Treatment:...

  • Page 102: Marking

    [AK4493] ■ Marking AK4493EQ ￥0VT XXXXXXX 1) Pin #1 indication 2) Date Code: XXXXXXX (7 digits) 3) Marking Code: AK4493EQ 4) AKM Logo 017012230-E-00 2017/12 - 102 -...
  • Page 103 [AK4493] 12. Ordering Guide ■ Ordering Guide 40  +85C AK4493EQ 48-pin LQFP (0.5mm pitch) AKD4493 Evaluation Board for AK4493 13. Revision History Date (Y/M/D) Revision Reason Page Contents 17/12/05 First Edition 017012230-E-00 2017/12 - 103 -...
  • Page 104 [AK4493] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products.

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