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AsahiKASEI AK5602A Manual

Energy metering lsi for multi phase, high accurate application
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Energy Metering LSI for multi phase, high accurate application
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Suitable for three phase, 3 wired or 4 wired
energy metering or energy monitoring application
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Provide less than 0.1 % active & reactive energy
error over a dynamic range of 1000 to 1,
compatible with IEC 0.5S
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Provide instantaneous active power, reactive
power and apparent power
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Provide voltage RMS, current RMS, voltage
instantaneous value, current instantaneous value
and power factor in each phase.
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Provide less than 0.5 % voltage RMS, current
RMS and power factor error
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Provide very accurate 90 degree phase shifter over
45Hz to 65Hz input frequency range, which is
used for reactive power calculation
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Provide minute input voltage monitoring function
Wide phase adjust. range between V & I (11 °)
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Provide positive and negative power indication
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Built-in temperature sensor
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Single power supply (3 V or 5V)
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48LQFP
Φ Φ
MS1285-E-00
V
Φ
- 1 -
AK5602A is one of the most advanced and functional
LSIs for multi phase energy measurement.
Current and voltage signals through CT, Hall sensor, or
Shunt Resistors are converted into digital signal with
18bit ADC.
Instantaneous voltage and current in each phase is
multiplied and is added in total phases.
The value changes into active power after passing
through LPF and added with the value of a light load
register. After this value is compared with the value of
rated standard value register, it outputs pulses in
proportion to the calculation.
Regarding reactive power, input current is precisely
shift by 90 degree and multiplied with respective voltage
input signal. It outputs pulses in the same manner of
active power calculation.
And apparent power can be selectively derived from
either active power and reactive power calculation or
VRMS x IRMS calculation and it outputs pulses as the
result of calculation.
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a
[AK5602A]
AK5602A
± °
°
2011/02

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Summary of Contents for AsahiKASEI AK5602A

  • Page 1 Energy Metering LSI for multi phase, high accurate application ” Suitable for three phase, 3 wired or 4 wired AK5602A is one of the most advanced and functional energy metering or energy monitoring application LSIs for multi phase energy measurement.
  • Page 2 [AK5602A] Ich 1 Gain RPST Active Adj. XP+RPL Power to Frequency TPST Gain XP+TPL Conversion x1 to x32 Ich 2 Adj. 90 degree Sigma- Phase phase Delta Adj. shifter Mod. Apparent Ich 3 Value Power RQST Reactive Calculation Power XQ+RQL...
  • Page 3 [AK5602A] Current Input Gain selection (from ×1 to ×32) Voltage Input Gain selection (from ×1 to ×4) (Programmable Gain Amp) This PGA becomes operative with RST = STBY = “H” Sigma Delta Sigma Delta Modulator with 3 channel differential inputs.
  • Page 4 This block becomes operative with RST = STBY = DIS = “H” Temperature sensor This block measures the temperature of AK5602A. This block becomes operative with RST = STBY = DIS = “H” Frequency pulse...
  • Page 5 [AK5602A] AI : Analog input DI : Digital input PWR : Power AO : Analog output DO : Digital output GND : Ground Reset input ( Schmitt trigger input ) All circuits become inoperative with “L” level input. registers including...
  • Page 6 [AK5602A] DVSS Digital ground. DVDD Digital power. Negative active energy pulse output. “H” pulse is output when accumulated negative active power value is over the setting standard value. This pin becomes inoperative when RST = “L” or STBY = “L” or DIS = “L”.
  • Page 7 [AK5602A] VREFI Reference voltage input. It usually connects to VREFO. An outside VREF is connected between this pin and AVSS in a case that an inside VREF of the IC is not used. VCOM Common voltage output, 1.17V. It feeds a common voltage to an internal block of the IC.
  • Page 8 [AK5602A] Serial interface selection input (Schmitt trigger input) Serial interface become operative with “L” level input at this pin while RST = “H”. SCLK Serial data clock input BVSS Silicon base reference GND. Connects to AVSS. DVSS Digital ground. DVDD Digital power.
  • Page 9 [AK5602A] Power supply voltage DVDD -0.3 +6.5 AVDD -0.3 +6.5 Ground level AVSS DVSS Voltage reference level BVSS ±10 Input current Except power pin Analog input -0.3 (AVDD)+0.3 INA1 voltage1 Analog input -3.0 +3.0 I1P, I1N, I2P, INA2 voltage2 I2N, I3P, I3N,...
  • Page 10 [AK5602A] Power supply AVDD 5.25 voltage Note 1 DVDD 5.25 Analog reference input voltage 1.11 1.17 1.23 Note 2 Analog input maximum voltage -1.0 Note 3 Analog input Note 4 voltage °C Operating temperature Note 1: -0.1V ≤ DVDD - AVDD ≤ +0.1V Note 2: This is a case when outside reference voltage is connected to VREFI.
  • Page 11 [AK5602A] Conditions: Ta=25°C, AVDD=DVDD=5.0V, 1.17V, XCLK = 12.9024MHz, REF = Signal frequency = 50Hz, Measured bandwidth = 10 to 1.5kHz; Unless otherwise specified. Voltage side Input range Gain setting : ×4 (12 dB) ±0.25 Note 5 ×2 (6 dB) ±0.5 ×1 (0 dB)
  • Page 12 [AK5602A] Resolution S/N+D Note 9 Isolation between Note 10 current and voltage Crosstalk between voltage channels Power factor adjustment -613.84 613.84 Note 11 range between current and voltage Power factor adjustment accuracy between 1.24 Note 12 current and voltage ADC period 3.15...
  • Page 13 [AK5602A] Resolution S/N+D Note 14 Isolation between Note 15 current and voltage Crosstalk between current channels ADC period 3.15 Note 16 Note 14: This is the value when analog input signal is applied at -6dB of full scale value with PGA = 0 dB.
  • Page 14 [AK5602A] Power consumption Note 21 Standby Current Note 21 Note 21: TYP1 is the value at AVDD = DVDD = 3.0V and TYP2 is the value at AVDD = DVDD = 5.0V. Consumption current is measured on condition of which all digital inputs are connected to DVDD or DVSS and all analog inputs are connected to analog input bias level.
  • Page 15 [AK5602A] Phase shift 45 to 66Hz 89.98 90.02 degree Note 22 value ± 0.001 Gain error 0 to 1500Hz Note 23 Note 22: Phase difference between two inputs. Note 23: Gain error between input and output of 90 degree phase shifter.
  • Page 16 [AK5602A] Ta=-40 to 85°C, AVDD=DVDD=2.7~5.25V, CL=20pF, XCLK=12.9024MHz Serial Clock Frequency SCLK SCLK “H” pulse width SCLK Fig.1 SCKH RPO,TPO 59.5 Fig.3 OUTH ±0.2 RQO,TQO Note 25 “L” pulse width SCLK Fig.1 SCKL RSTL Fig.4 STBL STBY DISL Hold time CS→SCLK CCKH Fig.1...
  • Page 17 [AK5602A] In writing 0.7DVDD 0.3DVDD CCKH SCKH CCKS 0.7DVDD SCLK 0.3DVDD CKDS CKDH SCKL 0.7DVDD 0.3DVDD Fig.1 In reading 0.7DVDD 0.3DVDD CCKH SCKH CCKS 0.7DVDD SCLK 0.3DVDD CKDZ CKDV SCKL High-Z High-Z Fig.2 OUTH 0.7DVDD 0.3DVDD STBY RSTL Fig.3 STBL Fig.4...
  • Page 18 [AK5602A] Operation of all circuits including serial interface and oscillator circuits is halted and digital circuits including input / output register, control register and data register are initialized. At the same time F1, F2, F3, RPO, TPO, RQO,TQO, TPST, RQST and TQST becomes “L”...
  • Page 19 [AK5602A] It is possible to access a serial interface circuit with RST = “H”, CS = “L”. By applying a serial clock at SCLK pin, input data is written into an input shift register. Input data consists of 7 bits of address, one bit “L” level writing command and 16 bits data strings.
  • Page 20 [AK5602A] It is possible to access a serial interface circuit with RST = “H”, CS = “L”. By applying a serial clock at SCLK pin, input data is written into an input shift register. Input data consists of 7 bits of address, one-bit “H” level reading command is followed.
  • Page 21 [AK5602A] Initial value of controlling registers below is set to comply with Japanese standard. In a case that the LSI is used to comply with IEC standard, initial value of some registers should be modified. Please refer to the chapter 5.5, which describes the way of the system calibration in IEC mode.
  • Page 22 [AK5602A] V1AD V(voltage)1 instantaneous value 0000h V2AD V(voltage)2 instantaneous value 0000h V3AD V(voltage)3 instantaneous value 0000h I1HAD I(current)1 instantaneous value (upper bits) 0000h I2HAD I(current)2 instantaneous value (upper bits) 0000h I3HAD I(current)3 instantaneous value (upper bits) 0000h ILAD I1/I2/I3 instantaneous value (lower bits)
  • Page 23 [AK5602A] S1 apparent power 0000h S2 apparent power 0000h S3 apparent power 0000h 0000h SSUM Total apparent power 0000h Reserved 0000h RXPO RPO active power accumulated value 0000h TXPO TPO active power accumulated value 0000h RXQO RQO reactive power accumulated value...
  • Page 24 [AK5602A] RPR15-8 9999h (R/W) RPR7-0 RPR25-24 00C9h (R/W) RPR23-16 TPR15-8 9999h (R/W) TPR7-0 TPR25-24 00C9h (R/W) TPR23-16 RQR15-8 9999h (R/W) RQR7-0 RQR25-24 00C9h (R/W) RQR23-16 TQR15-8 9999h (R/W) TQR7-0 TQR25-24 00C9h (R/W) TQR23-16 TQST3-0 RQST3-0 1111h (R/W) TPST3-0 RPST3-0 B2B11-8...
  • Page 25 [AK5602A] PGAI1_5-0 0401h (R/W) PGAV1_2-0 PGAI2_5-0 0401h (R/W) PGAV2_2-0 PGAI3_5-0 0401h (R/W) PGAV3_2-0 VTHF1_7-0 2B2Dh (R/W) VTHR1_7-0 VTHF2_7-0 2B2Dh (R/W) VTHR2_7-0 VTHF3_7-0 2B2Dh (R/W) VTHR3_7-0 FULI1_7-0 0000h (R/W) FULV1_7-0 FULI2_7-0 0000h (R/W) FULV2_7-0 FULI3_7-0 0000h (R/W) FULV3_7-0 VOFF15-8 0000h (R/W)
  • Page 26 [AK5602A] ZSI3 ZSI2 ZSI1 ZSV3 ZSV2 ZSV1 0000h (R/W) PFSEL SSEL TEMP FULLI FULLV INVALID 0000h (R/W) RMSRD1-0 ADRD1-0 RDY1-0 V1AD15-8 0000h V1AD7-0 V2AD15-8 0000h V2AD7-0 V3AD15-8 0000h V3AD7-0 I1AD17-10 0000h I1AD9-2 I2AD17-10 0000h I2AD9-2 I3AD17-10 0000h I3AD9-2 0000h I3AD1-0...
  • Page 27 [AK5602A] P1_15-8 0000h P1_7-0 0000h P1_19-16 P2_15-8 0000h P2_7-0 0000h P2_19-16 P3_15-8 0000h P3_7-0 0000h P3_19-16 PSUM15-8 0000h PSUM7-0 0000h PSUM21-16 Q1_15-8 0000h Q1_7-0 0000h Q1_19-16 Q2_15-8 0000h Q2_7-0 0000h Q2_19-16 Q3_15-8 0000h Q3_7-0 0000h Q3_19-16 QSUM15-8 0000h QSUM7-0 0000h...
  • Page 28 [AK5602A] PTOTR15-8 0000h PTOTR7-0 0000h PTOTR23-16 PTOTT15-8 0000h PTOTT7-0 0000h PTOTT23-16 QTOTR15-8 0000h QTOTR7-0 0000h QTOTR23-16 QTOTT15-8 0000h QTOTT7-0 0000h QTOTT23-16 PPULSE13-8 0000h PPULSE7-0 QPULSE13-8 0000h QPULSE7-0 S1_15-8 0000h S1_7-0 S2_15-8 0000h S2_7-0 S3_15-8 0000h S3_7-0 SSUM15-8 0000h SSUM7-0 0000h...
  • Page 29 [AK5602A] RXPO15-8 0000h RXPO7-0 TXPO15-8 0000h TXPO7-0 RXQO15-8 0000h RXQO7-0 TXQO15-8 0000h TXQO7-0 PF1_14-8 0000h PF1_7-0 PF2_14-8 0000h PF2_7-0 PF3_14-8 0000h PF3_7-0 0080h TEMP7-0 TCOEF12-8 1C2Ah (R/W) TCOEF7-0 0000h (R/W) TOFFSET4-0 MS1285-E-00 2011/02 - 29 -...
  • Page 30 [AK5602A] RPR15-8 (Same as below) 9999h (R/W) RPR7-0 (Rated active power threshold value at receiving mode) RPR25-24 (Same as below) 00C9h (R/W) RPR23-16 (Rated active power threshold value at receiving mode) TPR15-8 (Same as below) 9999h (R/W) TPR7-0 (Rated active power threshold value at transmitting mode)
  • Page 31 [AK5602A] 0.70 When “L” level pulse width at RPO pin is narrower than the starting power threshold value, the level at RPST 0.75 pin becomes “H” level at the next rising edge of RPO 0.80 pulse. 0.85 When “L” level pulse width at RPO pin is wider than the 0.90...
  • Page 32 [AK5602A] 0.70 When “L” level pulse width at TQO pin is narrower than the starting power threshold value, the level at 0.75 TQST pin becomes “H” level at the next rising edge 0.80 of TQO pulse. 0.85 When “L” level pulse width at TQO pin is wider than 0.90...
  • Page 33 [AK5602A] 09h (R/W) B2 balance value X000h 0Ah (R/W) B3 balance value X000h B2 balance value: the value to adjust the gain of V2 against V1 B3 balance value: the value to adjust the gain of V3 against V1 The gain can be adjusted from 0 times to (2-1/2048) times.
  • Page 34 [AK5602A] 0Bh(R/W) RQ light load value RP light load value 0000h 0Ch(R/W) TQ light load value TP light load value 0000h RP light load value, RQ light load value: the value is used to adjust the offset at RP side or RQ side in light load mode.
  • Page 35 [AK5602A] PFCN1_9-8 (N1_Adj.) 0000h (R/W) PFCN1_7-0 (N1_Adj.) PFCN2_9-8 (N2_Adj) 0000h (R/W) PFCN2_7-0 (N2_Adj) PFCN3_9-8 (N3_Adj) 0000h (R/W) PFCN3_7-0 (N3_Adj) N1_Adjust: This value is used to delay the starting point of AD conversion at voltage side against current side in the AD conversion of [ (I1P) – (I1N), (V1P) – (VIN) ].
  • Page 36 [AK5602A] PGAI1_5-0 (CH1 current side PGA) 0401h (R/W) PGAV1_2-0 (CH1 voltage side PGA) PGAI2_5-0 (CH2 current side PGA) 0401h (R/W) PGAV2_2-0 (CH2 voltage side PGA) PGAI3_5-0 (CH3 current side PGA) 0401h (R/W) PGAV3_2-0 (CH3 voltage side PGA) PGAV1 (bit2 – 0): to select CH1voltage side PGA ±1.0V...
  • Page 37 [AK5602A] PGAV2 (bit2-0): to select CH2 voltage side PGA ±1.0V ±1.0V ±0.5V ±0.333V ±0.25V PGAI2 (bit13-8): to select CH2 current side PGA ±1.0V ±1.0V ±0.5V ±0.333V ±0.25V ±0.20V ±0.125V ±0.0833V ±0.0556V ±0.0417V ±0.0323V ±0.03125V PGAV3 (bit2-0): to select CH3 voltage side PGA ±1.0V...
  • Page 38 [AK5602A] PGAI3 (bit13-8): to select CH3 current side PGA ±1.0V ±1.0V ±0.5V ±0.333V ±0.25V ±0.20V ±0.125V ±0.0833V ±0.0556V ±0.0417V ±0.0323V ±0.03125V VTHF1_7-0 (F1 falling threshold) 2B2Dh (R/W) VTHR1_7-0 (F1 rising threshold) VTHF2_7-0 (F2 falling threshold) 2B2Dh (R/W) VTHR2_7-0 (F2 rising threshold)
  • Page 39 [AK5602A] This is the falling threshold value of F1 output to determine the frequency based on AD conversion value of V1 (voltage input1). F1pin outputs ‘L’ level under the threshold value. The value should be 00h ≤ VTH1F ≤ 7Fh.
  • Page 40 [AK5602A] (1024+127)/1024 = 1.124023 (1024+126)/1024 = 1.123047 ∼ ∼ (1024+1)/1024 = 1.0009766 (256+0)/ 256= 1.00 (1024-1)/1024 = 0.999023 (1024-2)/1024 = 0.998047 ∼ ∼ (1024-127)/1024 = 0.875976 (1024-128)/1024 = 0.875 VOFF15-8 (V offset middle) 0000h (R/W) VOFF7-0 (V offset lower) 0000h...
  • Page 41 [AK5602A] QSSEL S3DIS S2DIS S1DIS Q3DIS Q2DIS Q1DIS 0000h (R/W) P3DIS P2DIS P1DIS This register enables the addition control of active power (P1/P2/P3), reactive power (Q1/Q2/Q3) and apparent power (S1/S2/S3) when power summation is executed. When ‘1’ is set to the corresponding bit, the addition of the corresponding channel is canceled.
  • Page 42 [AK5602A] ZSI3 ZSI2 ZSI1 ZSV3 ZSV2 ZSV1 0000h (R/W) PFSEL SSEL TEMP FULLI FULLV To set ‘1’ in this bit when the full-scale adjustment for voltage side is to be executed. When the adjustment is completed successfully, this bit becomes ‘0’ automatically.
  • Page 43 [AK5602A] INVALID 0000h (R/W) RMSRD1-0 ADRD1-0 RDY1 RDY0 : These bits assign RDY pin of the LSI to the one of the instantaneous value registers, RMS value registers or other read-only registers. ‘00’ (initial value) is for RMS registers,’01’ instantaneous registers, ’10’...
  • Page 44 [AK5602A] V1RMS15-8 (Higher bits of CH1 voltage RMS value) 0000h ( R ) V1RMS7-2 (Lower bits of CH1 voltage RMS value) V2RMS15-8 (Higher bits of CH2 voltage RMS value) 0000h ( R ) V2RMS7-2 (Lower bits of CH2 voltage RMS value)
  • Page 45 [AK5602A] Q1_15-8 (Higher bits of CH1 reactive power) 0000h ( R ) Q1_7-0 (Lower bits of CH1 reactive power) 0000h ( R ) Q1_19-16 (Highest bits of CH1 reactive power) Q2_15-8 (Higher bits of CH2 reactive power) 0000h ( R )
  • Page 46 [AK5602A] QTOTR15-8 (Higher bits of all total receiving reactive power) 0000h (R ) QTOTR7-0 (Lower bits of all total receiving reactive power) 0000h (R ) QTOTR23-16 (Highest bits of all total receiving reactive power) QTOTT15-8 (Higher bits of all total transmitting reactive power)
  • Page 47 [AK5602A] S1_15-8 (Higher bits of CH1 apparent power) 0000h ( R ) S1_7-0 (Lower bits of CH1 apparent power) S2_15-8 (Higher bits of CH2 apparent power) 0000h ( R ) S2_7-0 (Lower bits of CH2 apparent power) S3_15-8 (Higher bits of CH3 apparent power)
  • Page 48 [AK5602A] PF1_14-8(CH1 power factor) 0000h ( R ) PF1_7-0(CH1 power factor) PF2_14-8(CH2 power factor) 0000h ( R ) PF2_7-0(CH2 power factor) PF3_14-8(CH3 power factor) 0000h ( R ) PF3_7-0(CH3 power factor) These registers store power factors of CH1, CH2, CH3.Power factor is expressed by the value between -1 and +1.
  • Page 49 [AK5602A] 0080h TEMP7-0 (Temperature data) TEMP_COEF12-8 (Temperature gain coefficient) 1C2Ah (R/W) TEMP_COEF7-0 (Temperature gain coefficient) 0000h (R/W) TOFFSET4-0 (Temperature offset coefficient) Temperature related data are stored in these registers. It is possible to set TEMP bit (bit2) with ‘1’ of Function setting segister, ADD. ‘20h’ to measure the temperature of the LSI and the measured temperature data is written into Temperature register, ADD.
  • Page 50 [AK5602A] +15°C ∼ +1°C 0°C -1°C ∼ -16°C Measured temperature data is written into the Temperature data register,ADD.’57h’ after the temperature adjustment above is done against the value of temperature sensor. Gain can be set from ‘1’ to ‘4’ at voltage input side and ‘1’ to ‘32’ at current input side.
  • Page 51 [AK5602A] Calibration, offset adjustment of ADC will be started when CAL bit( bit7) of Function setting register,ADD.’20h’ is set ‘1’ under the condition of RST = STBY = “H”. It requires 4096 XCLKs to complete the calibration and ADC will be restarted after the calibration.
  • Page 52 [AK5602A] RDY signal for reading instantaneous values of ADC is set and output by setting RDY1-0 (bit1-0)=’01’ of the Control setting register, ADD. ‘21h’. When RDY becomes “L”, it means that accurate values of registers storing ADC’s value can be read out.
  • Page 53 [AK5602A] signal for reading RMS values of ADC is set and output by setting RDY1-0(bit1-0)=’00’ of Control setting register, ADD. ‘21h’. When RDY becomes “L”, it means that accurate values of registers storing ADC’s value can be read out. The low level of RDY is output while CH1’s ADC is executed after the ADC block has started under the condition of RST = STBY = “H”.
  • Page 54 [AK5602A] RDY signal for reading registers addressing ‘22h’ to ‘57h’ is set and output by setting RDY1-0 (bit1-0)=’10’ or ‘11’ of Control setting register, ADD. ‘21h’. When RDY becomes “L”, it means that accurate values of various registers can be read out.
  • Page 55 [AK5602A] It is possible to insert a HPF into voltage sides and current sides in order to remove DC components on input channels. This HPF is placed on a path after each ADC block. This means that DC components super imposed on as one part of an input signal and produced by an ADC block can be removed.
  • Page 56 [AK5602A] Phase Response 1000 Frequency [Hz] Fig.14 Phase –Frequency characteristics Phase Response Frequency [Hz] Fig.15 Phase – Frequency Characteristics (40Hz to 70Hz) MS1285-E-00 2011/02 - 56 -...
  • Page 57 [AK5602A] RMS calculation block calculates RMS value of V1, I1, V2, I2, V3 and I3 from ADC value. These values can be read from RMS registers. RMS calculation flow is shown in fig.16 (1) To calculate square value of V1 (I1, V2, I2, V3, I3)
  • Page 58 [AK5602A] XP+RPL or -XP+TPL data, which consists of significant 24bit, is supplied to active or reactive frequency converter at the rate of 3.15kHz. (note 1) Active or reactive power to frequency converter is making an arithmetic operation at the rate of 16/3 (16.8kHz) and produces RPO (RQO), TPO (TQO), RPST (RQST) and TPST (TQST) output.
  • Page 59 [AK5602A] 7FFFFFFh 0000000h underflow F000000h When ALU’s underflow occurs, the 28 bit register is reset. 59.5us (TPO, RQO, TQO) RPST (TPST, RQST, TQST) Fig.18 RPO (TPO, RQO, TQO) OUTPUT timing MS1285-E-00 2011/02 - 59 -...
  • Page 60 [AK5602A] The frequencies of voltage inputs are detected, being based on ADC value of V1, V2 and V3. For example, when the rising threshold value of F1, F2,and F3 is set at ‘3000h’ and the falling threshold value is set at ‘2000h’, the waveform will be shown below.
  • Page 61 Japanese standard of power metering specifies that 1000 of power pulses per one second should be output when rated input voltages and currents are applied to the system. AK5602A provides an easy calibration method to comply with the specification. By adjusting rated active or reactive power threshold value in receiving and transmitting side, the accuracy of the equipment would be attained.
  • Page 62 TPO, RQO, TQO). In this case, the inside timer of the AK5602A is used for one second timer and the value of the timer will be changed according to the frequency of using crystal.
  • Page 63 [AK5602A] 1. To set the starting power threshold value register ‘o’ second : ‘FFFFh’ at Starting power threshold value register,ADD. ‘08h’ 2. To set the accumulation frequency of IEC power pulse width setting register ‘4.2kHz’ : ‘8000h’ at IEC power pulse width setting register,ADD. ‘1Fh’...
  • Page 64 (RPO, TPO, RQO, TQO). In this case, the inside timer in the AK5602A is used for one second timer and the value of the timer will be changed according to the frequency of using crystal. AK5602A defines that one second timer is attained when 12.9024MHz crystal is used.
  • Page 65 α is equal to zero. When input signal frequency is 50Hz and using crystal frequency is 12.9024 MHz in AK5602A, the phase adjustment range, γ is expressed as followed. -613.84us ( -11.05 ° ) ≤ γ ≤ +613.84us (+11.05 ° ) It is possible to adjust the phase error with the resolution of 1.25us (0.0225 °...
  • Page 66 [AK5602A] 2.7V to 5.25V Example of Voltage inputs(Registors) 0.1uF 10uF sam e as sam e as V3 AVDD VREFI 33nF VREFO DVDD 10uF VCOM 0.1uF 33nF 0.1uF 0.1uF 4.7uF 0.1uF Power line (3phase 4line) Example of current inputs (CTs) sam e as...
  • Page 67 [AK5602A] 1) Shape: LQFP 2) Pin count: 48PIN 3) Marking: Marking of the package is specified as follows. a. No1 pin indication: There is a round mark and cutting edge. b. AKM’s logo and product name c. Date code XXXXXXX ( 7 digits)

  • Page 68: Important Notice

    [AK5602A] Revision History Date Revision Reason Page Contents 01/02/03 First edition IMPORTANT NOTICE ” These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products.