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SHEET 1 – CODEC
This sheet shows the audio codec, audio input and output circuitry, muting and power supplies for
the analogue section.
The design features analogue inputs for a record function, though the parts for this are not fitted
since the feature was removed from the product. 2 channels of audio are input on J3. Op-amp U3
and associated components form an input buffer having a gain of -0.4 and DC offset of +2V to
ensure the signal is at the correct levels for the codec. D3 and D8 provide limiting to ensure the
codec is not damaged in the event of large signal levels being applied. None of the components in
this section are fitted except C38 and C60; these have 0 ohm resistors fitted to ground the analogue
inputs of the codec.
U2 is a Cirrus Logic CS42406 audio codec. I2S audio is received from the CPU board for
conversion to analogue audio. I2S_TX0 and I2S_TX1 are the serial audio data for deck A and B
respectively. I2S_BCLK is the bit clock, I2S_LRCLK is the word clock and I2S_MCLK is the
master clock.
The codec is configured by software via the I2C signals SDA (data) and SCL (clock).
!DAC_RESET is used to reset the DAC (active low), and !ADC_RESET resets the ADC (also
active low).
4 analogue outputs from the codec are used for Deck A (left + right), and Deck B (left + right)
outputs. These are AC coupled by C29, C50, C54 and C26 to remove the 2V DC offset that the
signal has at the codec output.
nd
U1-A and associated components form a 2
order low pass butterworth filter, with corner frequency
of 50kHz approximately, and a gain of -1.25. All 4 output channels use the same circuit.
Q1-4 are muting transistors. When switched on, these clamp the audio outputs to ground, to ensure
no pops or clicks are heard at the output when the system is powered up or down.
The muting is controlled by the MUTEC1 output of the codec. When MUTEC1 is high, the outputs
will be muted. Transitors Q5-6 buffer the muting signal. R23 pulls the base resistors of Q1-4 down
to -4V to ensure the transistors are completely off when the system is not muted.
The MUTEC1 pin can be controlled by software to ensure that the system is muted when necessary.
MUTEC will always be high following power up, and the software waits until the codec has been
initialised before taking it low. This mutes pops and thumps during power up and initialisation. The
software also controls muting at power down, whether it is the user putting the unit into standby
mode, or the power is unplugged. In the latter case, the software receives a power fail signal to warn
it that the power is about to go away, and it mutes the system before any unpleasant noises are
heard.
The audio op-amps use +/-4V supply rails. The codec +VA supply also uses the +4V rail. U9 is a
low drop out voltage regulator that derives the +4V rail from the system +5V rail. U7 is a charge
pump voltage inverter that generates a -4V supply from the +4V rail.
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