Denon AVR-X8500H Service Manual page 162

fig.A03b
AVR-X8500/AV8805 DIGITAL AUDIO/NETWORK BLOCK DIRAGRAM
DIGITAL AUDIO BLOCK
Wireless Network
Input
Wired Network
Input
NET_VideoSignal(Clock/HS/VS/DE)
Netowrk Module
NET_VBUSdata(R:8bit/B:8bit/G:8bit)
USB-A
Z2NET_I2S
Input (FRONT)
iPod
Coprocessor
I2S/DSD_eARC
INPUT SPDIF_eARC
SPDIF_eARC
INPUT
I2S/DSD_HDMIRX
INPUT SPDIF_HDMIRX
SPDIF_HDMIRX
INPUT
I2S_HDMITX
OUTPUT
SPDIF_Z2HDMI
INPUT
NET_VideoSignal(Clock/HS/VS/DE)
OUTPUT
OUTPUT
NET_VBUSdata(R:8bit/B:8bit/G:8bit)
OPT1
OPT2
COAX1
COAX2
DENONLinkHD
8500 only
Jitter Reducer PLL
CS2100
FCXO-05 FCXO-05 FCXO-05
22.5792MHz 24.576MHz 25.0MHz
Ref clock Sel.
fs Assign Sel.
DENON Link HD
Generator Module
1/2 1/4
Div. Div.
I2S_NET DSP1 INPUT MUX
DSD_NET I2S_HDMIRX
1
DSD_HDMIRX
1
I2S_eARC
1
DSD_eARC
1
I2S_NET
1
DSD_NET
1
DIR_I2S
1
Z2NETADC I2S_HDMITX
Clock Generator
HDMI SPDIF
SELECTOR
SPDIF_eARC
SPDIF_HDMIRX
I2S_NET
ADCCLK
Main DIR
PCM9211
SDATA
I2S/DSD_eARC
SPDIF_HDMIRX
COAX1
COAX2
I2S/DSD_HDMIRX
OPT1 Z2NET_ADCINL
I2S_HDMITX OPT2
SPDIF_Z2HDMI Z2NET_ADCINR
SPDIF_Z2HDMI
OPT1
OPT2
COAX1
CLK
COAX2
Z2DIR_I2S
Z2_SPDIF
ZONE2 DIR
LC89091JA
Z2DAC_I2S
CLK
Z3DIR_I2S
Z3_SPDIF
ZONE3 DIR
LC89091JA
Z3DAC_I2S
162
DDR3 FLASH DDR3 FLASH
1st DSP 2nd DSP
ADSP-21573 ADSP-21573
DSP2 INPUT MUX
1
3
2
DAC INPUT MUX
1
2
3
2
2
2
2
2
2
2
ZONE2
Z2DAC_MUTE
Mute Logic
ZONE3 Z3DAC_MUTE
Mute Logic
6
7
MAIN DAC1
5
AK4490
3
1
2
6
7
MAIN DAC2
5
AK4490
3
1
2
6
7
MAIN DAC3
5
AK4490
3
1
2
6
7
MAIN DAC4
5
AK4490
3
Main ZONE
1
Mute Logic 2
6
7
MAIN DAC5
5
AK4490
3
1
2
6
7
MAIN DAC6
5
AK4490
3
1
2
6
7
MAIN DAC7
5
AK4490
3
1
2
6
Audio PLD
7
MAIN DAC8
5
5M570ZF256C5N
AK4490
3
1
2
ADC_CLK
MAIN ADC
SDATA
AK5358B
Z2DAC_MUTE
ZONE2 DAC
Z2DAC_I2S
PCM5100
Z3DAC_MUTE
ZONE2 DAC
Z3DAC_I2S
PCM5100
Z2NET_ADCINL
Z2NET_ADCINR
I2S_NET
NET DAC
PCM5100
DA_FL
OUTPUT
DA_FR
OUTPUT
DA_C
OUTPUT
DA_SW1
OUTPUT
DA_SW2
OUTPUT
DA_RSV
OUTPUT
DA_SL
OUTPUT
DA_SR
OUTPUT
DA_SBL
OUTPUT
DA_SBR
OUTPUT
DA_H1L
OUTPUT
DA_H1R
OUTPUT
DA_H2L
OUTPUT
DA_H2R
OUTPUT
DA_H3L
OUTPUT
DA_H3R
OUTPUT
ADIN_FL
INPUT
ADIN_FR
INPUT
Z2DA_L
OUTPUT
Z2DA_R
OUTPUT
Z3DA_L
OUTPUT
Z3DA_R
OUTPUT
Z2NET_ADCINL
INPUT
Z2NET_ADCINR
INPUT
NET_L
OUTPUT
NET_R
OUTPUT