Page 1 SC150 PMC & ½ Length PCI Hardware Reference Document No. D-T-MR-PMC#####-A-0-A6...
Page 3 Systran reserves the right to make changes without notice. Systran makes no warranty of any kind with regard to this printed material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose.
Page 4 This product is intended for use in industrial, laboratory or military environments. This product uses and emits electromagnetic radiation, which may interfere with other radio and communication devices. The user may be in violation of FCC regulations if this device is used in other than the intended market environments.
Page 5 TABLE OF CONTENTS 1. INTRODUCTION ..........................1-1 1.1 How To Use This Manual....................1-1 1.1.1 Purpose ......................1-1 1.1.2 Scope ........................1-1 1.1.3 Style Conventions....................1-1 1.2 Related Information......................1-1 1.3 Quality Assurance .......................1-1 1.4 Technical Support .......................1-2 1.5 Ordering Process .........................1-3 2. SCRAMNET OVERVIEW ........................2-1 2.1 Overview ..........................2-1 2.2 Shared Memory........................2-1 2.2.1 Dual-Port Memory Controller ................2-1...
Page 6 4.6.1 Fiber-optic configuration ...................4-5 4.6.2 Fiber-optic cables ....................4-5 4.6.3 Fiber-optic connection ..................4-6 4.7 Auxiliary Connection ......................4-7 4.8 Internal Configuration ......................4-7 4.8.1 SCRAMNet+ SC150 Control/Status Registers (CSR) .........4-7 4.8.2 EEPROM Initialization..................4-9 4.8.3 Node Identification....................4-9 4.8.4 Network Time-out ...................4-10 4.8.5 Memory Addressing ..................4-10 4.8.6 Shared Memory....................4-10...
Page 7 HOW TO USE THIS MANUAL APPENDICES APPENDIX A. SPECIFICATIONS......................A-1 APPENDIX B. CSR DESCRIPTIONS ....................B-1 APPENDIX C. CSR SUMMARY ......................C-1 APPENDIX D. CONFIGURATION AIDS ....................D-1 APPENDIX E. PASSIVE PMC CABINET KIT ..................E-1 APPENDIX F. ½ LENGTH PCI......................F-1 GLOSSARY..........................GLOSSARY-1 INDEX............................INDEX-1 Copyright 2003...
Page 8: Table Of Contents
Table 4-2 SCRAMNet+ SC150 Control/Status Registers................4-8 Table 4-3 EEPROM Table ........................4-9 Table 4-4 EEPROM Initialization......................4-9 Table 4-5 Byte Ordering Comparisons....................4-10 Table 5-1 SCRAMNet+ SC150 Message Contents ..................5-4 Table 5-2 ACR Functions.........................5-8 Table 5-3 Interrupt Controls ........................5-9 Table 5-4 Interrupt Error/Status Conditions.....................5-14 Table 5-5 General Purpose Counter/Timer Modes...................5-16...
Page 9 1.1 How To Use This Manual 1.1.1 Purpose This document is a reference manual for the SCRAMNet+ SC150 PMC host interface board. It provides a physical and functional description of the SCRAMNet+ SC150 PMC board. The manual describes how to unpack, set up, install and operate the hardware.
Page 10 Systran’s Quality System. BSI’s Quality Assurance division certified we meet or exceed all applicable international standards, and issued Certificate of Registration, number FM 31468, on May 16, 1995. The scope of Systran’s registration is: “Design, manufacture and service of high technology hardware and software computer communications products.”...
Page 11 INTRODUCTION 1.5 Ordering Process To learn more about Systran products or to place an order, please use the following contact information. Hours of operation are from 8:00 a.m. to 5:00 p.m. Eastern Standard/Daylight Time. • Phone: (937) 252-5601 or (800) 252-5601 •...
Page 12 INTRODUCTION This page intentionally left blank Copyright 2003 SC150 PMC H/W REFERENCE...
Page 13 SCRAMNet+ SC150 memory is automatically sent to the same SCRAMNet+ SC150 memory location in all nodes on the network. This is why it is also referred to as replicated shared memory. A good analogy is the COMMON AREA used by the FORTRAN programming language.
Page 14: Figure 2-1 Functional Diagram
SCRAMNET OVERVIEW Figure 2-1 Functional Diagram Copyright 2003 SC150 PMC H/W REFERENCE...
Page 15 SCRAMNET OVERVIEW 2.2.2 Control/Status Registers (CSRs) The operation of the SCRAMNet+ SC150 board is controlled by 16 Input/Output (I/O) CSRs. Address offsets for the CSRs can be found in Chapter 4, INSTALLATION. Most modes of operation are set during initialization in registers embedded in the PMC target controller, and remain unchanged during run time.
Page 16 2.4 Network Ring The SCRAMNet+ SC150 Network is a ring topology network. Data is transmitted at a rate of 150 Mbits/s over dual fiber-optic cables. The two lines together produce the incoming data clock. Due to the network speed and message slot size, the network can accommodate over 1,800,000 message slots passing by each node every second.
Page 17: Figure 2-2 Acr/Memory Access
Channeling is based on a user-controlled switch setting and may be toggled to the desired position by writing to a bit in the SCRAMNet+ SC150 CSR. When access to the ACR is enabled, shared memory is not accessible by the host and the ACR byte is viewed as the least significant byte (LSB) of every shared-memory four-byte address.
Page 18 SCRAMNET OVERVIEW SCRAMNet+ SC150 interrupts usually require a device driver to interface with the node processor. The driver is required primarily to permit the host processor to handle interrupts from the SCRAMNet device. 2.6.1 Network Interrupt Writes FOREIGN MESSAGE The node can receive a message from another node with the interrupt bit set. If Receive Interrupt Enable ACR[0] and Interrupt Mask Match Enable CSR0[5] are enabled, the data is written to shared memory and the address is placed on the Interrupt FIFO.
Page 19: Figure 2-3 Outgoing Interrupt
SCRAMNET OVERVIEW OUTGOING Address A22 - A0 D31 - D0 Data SHARED MEMORY D31 - D0 A22 - A0 Address Data D31 - D0 Interrupt Bit RING NETWORK RING LOGIC Figure 2-3 Outgoing Interrupt INCOMING INTERRUPT INTERRUPT FIFO A16 - A0 A22 - A16 SHARED MEMORY CSR 4...
Page 20 The network message interrupt bit does not need to be set. 2.7 External Triggers External triggers are not supported by the SCRAMNet+ SC150 PMC board. 2.8 General Purpose Counter/Timer The General Purpose Counter/Timer has six modes of operation controlled by CSR8 and CSR9, the output from the General Purpose Counter/Timer is stored in CSR13.
Page 21 2.9 LED Status Indicators 2.9.1 Network Access INSERT LED The green Insert LED is ON when the node is Inserted into the SCRAMNet+ SC150 Network ring. CARRIER DETECT LED The green Carrier Detect LED is ON when there is a valid pair of transmit lights from the previous SCRAMNet+ SC150 node into this node’s receiver pair.
Page 22 SCRAMNET OVERVIEW HIPRO WRITE The SCRAMNet+ SC150 network message is based on 32-bit longword data. This means if any 8-bit field of the 32-bit buffer is changed, the entire 32-bit message is transmitted. If a host is limited to only 8-bit or 16-bit data-bus transactions the network throughput is quartered or halved, respectively.
Page 23 This can be useful for synchronization. This means that when the host performs a write to the SCRAMNet+ SC150 shared memory, this data is not immediately written to the host node’s memory, but is first sent to the other nodes on the network.
Page 24 SCRAMNET OVERVIEW This page intentionally left blank Copyright 2003 2-12 SC150 PMC H/W REFERENCE...
Page 25 This manual covers both the SCRAMNet+ SC150 PMC and the ½ Length PCI boards. See Appendix F for details on the ½ Length PCI. The SCRAMNet+ SC150 interface node board is backwards compatible with the original SCRAMNet Classic product with the exception of the GOLD Ring communication protocol.
Page 26: Figure 3-1 Sc150 Pmc Board
Variable-length message packet capability. • Dual-port memory. • Dual memory and error interrupt. 3.5 PMC Specification Level The SCRAMNet+ SC150 PMC board was designed in accordance with the PCI Local Bus Specification 2.1. 3.6 Hardware • 32-bit PMC compliant •...
Page 27 1 MB. The SCRAMNet+ SC150 Diagnostic software executable is 386/486 compatible. It requires 2 MB of system memory (excluding SCRAMNet+ SC150 memory), and runs under MS-DOS 3.3 and above; and all 386 DPMI level .9 compliant host memory managers, including the 386 enhanced mode of Microsoft Windows 3.1.
Page 28: Figure 3-2 Node Inclusion And Isolation
PRODUCT OVERVIEW 3.9.3 SCRAMNet Monitor The SCRAMNet Monitor allows viewing and editing of memory and CSR locations on the SCRAMNet node. This utility is useful during software development to verify that the correct values are being written to SCRAMNet memory and CSRs. 3.10 Options 3.10.1 Quad Switch The SCRAMNet Quad Switch is designed to provide configuration control over the...
Page 29 PRODUCT OVERVIEW The Quad Switch can also perform media conversion. Since each port has a Media Card just like a SCRAMNet node, each port can be configured to handle coax, standard link or long link fiber. This allows a signal to arrive on one media type, and go out on another. Visually, LED’s signify the state of node inclusion in the ring and if carrier is detected.
Page 30 PRODUCT OVERVIEW This page intentionally left blank Copyright 2003 SC150 PMC H/W REFERENCE...
Page 31 Remove the PMC anti-static bag from the carton. • Open the anti-static bag and remove the PMC host card. Save the shipping material in case the SCRAMNet+ SC150 board needs to be returned. The optional fiber-optic cables and Fiber Optic Bypass Switch are shipped in separate cartons.
Page 32: Figure 4-1 Pmc Layout (Bottom View)
INSTALLATION Controller EEPROM (U1) Connectors (P1, P2) EEPROM write Enable/ Disable (J303) EEPROM read Enable/ Disable (J3O4) Insert and 3-Pin Carrier Detect Auxiliary LEDs Connector Receivers Transmitters (J1) Figure 4-1 PMC Layout (Bottom View) Copyright 2003 SC150 PMC H/W REFERENCE...
Page 33: Figure 4-2 Eeprom Write (J303)
INSTALLATION 4.3.1 DEC-specific Board If the board is a DEC-specific board: • it has the part number H-AS-DPMCDXXX-X0 (where “X” varies with memory and media options) • EEPROM U1 is labeled: V962 (Where # stands for the EEPROM revision) • The U6 chip is labeled “PMCDEC.A#”...
Page 34: Figure 4-3 Eeprom Read (J304)
INSTALLATION SET/VERIFY EEPROM READ (J304) ENABLE DISABLE EEPROM READ Figure 4-3 EEPROM read (J304) To enable EEPROM read install a 2-pin header on the left pair of the read jumper as viewed from the fiber-optic connector end of the board. Factory default: ENABLED 4.5 Install the Board Node configuration is pre-set or defined in the PMC Configuration File.
Page 35: Figure 4-5 Fiber Optic St Connector
The optional paired fiber-optic cables are shipped in a separate carton. The fiber-optic cables are to be attached to the connectors on the SCRAMNet+ SC150 board or on the Cabinet Kit, as appropriate. Remove the rubber boots on the fiber optic transmitters and receivers as well as the ones on the fiber-optic cables.
Page 36: Figure 4-6 Fiber-Optic Connections
INSTALLATION FIBER-OPTIC CABLE PRECAUTIONS Fiber-optic cables are made of glass and may break if crushed or bent in a loop with less than a 2-inch radius. Perform a visual check of the cable ends before inserting into the Media Card connector. If debris is inserted into the transmitter/receiver connector it may not be possible to clean it out or could result in damage to the transmitter or receiver lens.
Page 37: Figure 4-7 Pmc Faceplate With Auxiliary Connection
4.8.1 SCRAMNet+ SC150 Control/Status Registers (CSR) Table 4-2 is a listing of the SCRAMNet+ SC150 Control/Status Registers. If using software other than that supplied by Systran, the offsets in the first two columns must be added to the 0x800000 CSR base address.
Page 38: Table 4-2 Scramnet+ Sc150 Control/Status Registers
INSTALLATION Table 4-2 SCRAMNet+ SC150 Control/Status Registers Byte Shortword Alias Size Active Type Register Offset Offset (Bytes) Bits Description CSR0 General SCRAMNet+ SC150 Enable and Reset 0x100 0x80 CSR1 SCRAMNet+ SC150 Error Indicators 0x206 0x103 CSR2 General SCRAMNet+ SC150 Control...
Page 39: Table 4-3 Eeprom Table
The EEPROM is used to store the initial power-up register values. The EEPROM can be programmed either over the host backplane or by most PROM programmers. An EEPROM initialization (EPI) program is included in the Systran Software Utilities Package for most systems.
Page 40: Table 4-5 Byte Ordering Comparisons
There must be a non-contiguous “gap” between system memory and the SCRAMNet+ SC150 PMC board shared-memory address. For example, if the system has 12 MB of RAM, and the SCRAMNet+ SC150 PMC board is configured with 4 MB, the address for the board would be at the 16 MB boundary.
Page 41 If this message does not appear, the Register base address, memory base address and/or memory size may be incorrect. All SCRAMNet+ SC150 nodes in the fiber optic network ring must be powered on unless they have Fiber Optic Bypass Switches or Quad Switches installed.
Page 42 INSTALLATION This page intentionally left blank Copyright 2003 4-12 SC150 PMC H/W REFERENCE...
Page 43 For interrupt-driven applications, an interrupt service routine (ISR) is required to handle the interrupts triggered by the SCRAMNet+ SC150 node. An example of a generic ISR is included Figure 5-11, page 5-28 at the end of this section.
Page 44: Figure 5-1 Memory Sharing With Virtual Paging
For example: 12340 + 400000 = 412340 This network address is then transmitted to all of the SCRAMNet+ SC150 nodes and is written to that address. In nodes where the address does not exist in SCRAMNet+ SC150 memory, the write is ignored.
Page 45 CSRs and a brief identification of each bit. 5.3 Initialization The initialization of the SCRAMNet+ SC150 node from a cold boot is determined by the settings of the EEPROM. No fiber-optic cable connections are required to perform a read/write to the local host’s SCRAMNet+ SC150 memory.
Page 46: Table 5-1 Scramnet+ Sc150 Message Contents
OPERATION NOTE: All SCRAMNet+ SC150 nodes in the fiber optic network ring must be powered on unless they have a fiber optic bypass switches or Quad Switches installed. 5.4 Basic Send/Receive Configuration The minimum configuration that allows basic send and receive operation is accomplished without interrupts.
Page 47 Bits A0 and A1 are always zero for a longword boundary. DATA VALUE This 32-bit field contains the data value in SCRAMNet+ SC150 memory that is currently being updated around the ring. When the PLUS mode is enabled, data size may vary up to 256 bytes or 1024 bytes depending on the option selected.
Page 48 To maintain a PLUS mode transmission, step 1 requires that new data is written to the SCRAMNet+ SC150 board at a rate greater than or equal to 16.7 MB/sec (this is a 32-bit write every 240 ns). Any delay in the host data write will result in failure of step 1, and a premature end to the PLUS mode transmission.
Page 49 5.11.4 for more information). SHARED-MEMORY WRITE SCRAMNet+ SC150 shared-memory is based upon a 32-bit word. If an 8- or 16-bit write occurs from the host system, then the 32-bit word that contains that 8- or 16-bit write is sent on the network. Therefore, it is important that other nodes do not simultaneously modify other 8- or 16-bit segments within that 32-bit word.
Page 50: Table 5-2 Acr Functions
ACR bytes can no longer be accessed while the ACR Enable bit is zero. In order for the ACR values to take effect for interrupt action, the following SCRAMNet+ SC150 CSR actions should be considered for the type of interrupt operation desired: •...
Page 51: Table 5-3 Interrupt Controls
OPERATION 5.7 Interrupt Controls SCRAMNet+ SC150 allows a processor to receive interrupts from and/or transmit interrupts to any other processors on the network, including the originating processor. Table 5-3 indicates the various sources for interrupt control. 5.7.1 Interrupt Options Table 5-3 Interrupt Controls...
Page 52 Receive Interrupt Enable ACR[0] bit set for that address will generate an interrupt signal to their host processor. The host issues a write to SCRAMNet+ SC150 shared memory. If Override TIE CSR0[9] or ACR TIE ACR[1] is set and Network Interrupt Enable CSR0[8] is set, then the interrupt message is transmitted (INT = 1).
Page 53: Figure 5-2 Transmit Interrupt Logic
OPERATION HOST TRANSMIT ENABLE WRITE CSR0[1] MUST BE ACTIVE CSR0[9] OVERRIDE TIE ACR[1] CSR0[8] NETWORK INTERRUPT ENABLE TRANSMIT TRANSMIT INTERRUPT SLOT TO NON-INTERRUPT NETWORK SLOT TO NETWORK Figure 5-2 Transmit Interrupt Logic Copyright 2003 5-11 SC150 PMC H/W REFERENCE...
Page 54 CSR8. MASKED OR SELECTED The masked or selected method requires choosing SCRAMNet+ SC150 shared-memory locations on each node to receive and/or transmit interrupts. These shared-memory locations may also be used to generate signals to external triggers. The procedure for selecting shared-memory locations for interrupts and/or external triggers is explained in paragraph 5.6: Auxiliary Control RAM.
Page 55: Figure 5-3 Receive Interrupt Logic
OPERATION CSR1 NETWORK MESSAGE PACKET ERROR CSR0[7] CSR2[9] WRITE NATIVE INT ON OWN SLOT ERRORS CSR2[10] ENB INT ON Rx IN SLOT CSR8[10] RECEIVE OVERRIDE INTERRUPT MESSAGE CSR0[6] CSR9 OVERRIDE ERROR MASK BIT ACR[0] CSR0[5] MASK INTERRUPT TO MATCH HOST CSR0[3] PLACE HOST...
Page 56: Table 5-4 Interrupt Error/Status Conditions
OPERATION 5.8.2 Network Error The second interrupt condition is designed to intercept network errors. CSR1 contains the following error conditions that may be masked by CSR9: Table 5-4 Interrupt Error/Status Conditions Interrupt Transmit FIFO Full Transmit FIFO Not Empty Transmit FIFO O Full (Not masked for errors) Interrupt FIFO Full Protocol Violation...
Page 57 The Interrupt FIFO is accessed via CSR4 and CSR5. CSR5 contains the most significant seven bits of the 23-bit SCRAMNet+ SC150 interrupt address and CSR4 contains the remaining 16 bits of the interrupt address. (The 23-bit address allows for future expansion of memory).
Page 58: Table 5-5 General Purpose Counter/Timer Modes
OPERATION 5.10.1 Available Modes The SCRAMNet+ SC150 General Purpose Counter/Timer register (CSR13) can be used as a counter or a timer. The mode is selected by a combination of registers and bits explained on page 5-13. Table 5-5 describes the counter/timer modes available:...
Page 59 If CSR0[11] is OFF and CSR0[10] is ON, only the address space above 4 K bytes of SCRAMNet+ SC150 memory is data-filtered. If both bits 11 and 10 are ON, all SCRAMNet+ SC150 memory is data-filtered. In either case, CSR0[10] must be ON for any data filtering to take place on that node.
Page 60: Figure 5-4 Data Filter Logic
OPERATION DATA FILTER LOGIC NOTHING WRITE HOST DATUM SAME DATUM WRITE TO MEMORY READ SHARED MEMORY NETWORK RING NETWORK RING NETWORK LOGIC Figure 5-4 Data Filter Logic Copyright 2003 5-18 SC150 PMC H/W REFERENCE...
Page 61 OPERATION HIPRO mode is selected for those memory addresses which have ACR[4] set. HIPRO Enable CSR2[13] must also be set. Use a non-HIPRO location write to synchronize the HIPRO flags. 5.11.3 Loopback Modes Each node has a Monitor and Bypass mode, Wire Loopback mode, Mechanical Switch Loopback mode, and a Fiber Optic Loopback mode.
Page 62: Figure 5-5 Monitor And Bypass Mode
OPERATION MONITOR AND BYPASS MODE This mode permits the node to receive data only. Network data is not re-transmitted. Table 5-6 Monitor and Bypass Mode States State Register Setting Receive Enable CSR0[0] Transmit Enable CSR0[1] DON’T CARE Insert Enable CSR0[15] Enable Wire Loopback CSR2[7] Fiber Optic Bypass Switch...
Page 63: Figure 5-6 Wire Loopback Mode
OPERATION WIRE LOOPBACK MODE The Wire loopback permits testing of the internal circuitry and needs no manual external modifications to work. In this mode, the transmitted signal does not leave the board. Table 5-7 Wire Loopback Mode States State Register Setting Receive Enable CSR0[0]...
Page 64: Figure 5-7 Mechanical Switch Loopback Mode
OPERATION MECHANICAL SWITCH LOOPBACK MODE This mode permits testing of all circuitry up to and including a major portion of the Media Card. Table 5-8 Mechanical Switch Loopback Mode States State Register Setting Receive Enable CSR0[0] Transmit Enable CSR0[1] Insert Enable CSR0[15] Enable Wire Loopback CSR2[7]...
Page 65: Figure 5-8 Fiber Optic Loopback Mode
OPERATION FIBER-OPTIC LOOPBACK When this mode is invoked, the output of the transmitter is connected by fiber optics directly to the input of the receiver, and the receiver is disconnected from the network. Table 5-9 Fiber-Optic Loopback Mode States State Register Setting Receive Enable...
Page 66: Table 5-10 Node Insert Mode
OPERATION The optional Fiber Optic Bypass Switch must be installed for this to work. However, in the absence of the Fiber Optic Bypass Switch, fiber-optic cables could be run from the node’s transmitter output connectors to the receiver input connectors. This configuration, with Insert Node enabled, constitutes a Fiber Optic Loopback mode for stand-alone testing.
Page 67: Figure 5-9 Insert Mode
SC150 memory faster than the network can absorb the data. If a CPU is capable of writing to the SCRAMNet+ SC150 memory on the PMC bus at such a rate that the Transmit FIFO becomes full (1024 deep), data could be lost. In the event that the...
Page 68 OPERATION Figure 5-10 Quad Switch Copyright 2003 5-26 SC150 PMC H/W REFERENCE...
Page 69 When the host performs a write to the SCRAMNet+ SC150 shared-memory, it is not immediately written to the host memory, but is first sent to the other SCRAMNet+ SC150 nodes on the network. Set CSR2[8] and CSR2[9] to enable the Write-Me-Last mode. If desired, this mode can also be used to generate interrupts to the originating node by setting CSR2[10] as well.
Page 70: Figure 5-11 Interrupt Service Routine
OPERATION CSR0 IMME and HIE must be set in order to re-arm interrupts. CSR1 Bits 0-15 contain various error and status conditions. Interrupts are re-armed whenever any value is written to CSR1. CSR4 Bits 0-15 contain the interrupt address bits A0-A15. CSR5 Bits 0-6 contain the interrupt address bits A22-A16.
Page 71 A A - SPECIFICATIONS APPENDIX A SPECIFICATIONS TABLE OF CONTENTS A.1 Hardware Specifications........................A-1 A.2 Performance.............................A-2 A.3 Part Number ............................A-2 A.4 Board Dimensions..........................A-3 A.5 PMC Bus Voltage Specification .......................A-4 A.6 Fiber Optic Bypass Switch .......................A-5...
Page 73 SPECIFICATIONS A.1 Hardware Specifications Hardware Compatibility:........... PCI local bus specification, rev. 2.1 Draft standard for a common mezzanine card family: CMC (IEEE P1386/Draft 2.0) Draft standard physical and environmental layers for PCI Mezzanine cards: PMC (IEEE P1386/Draft 2.0) Physical Dimensions: PMC Card ............
Page 74 SPECIFICATIONS A.2 Performance Table A-1 Data Performance Table* DMA PERFORMANCE in V3 from V3 from MBytes/s with the data flow SCRAMNet SCRAMNet direction Prefetching Prefetching Toward Network/From Network SCRAMNet Write Posting on 16.6/15.0 16.6/15.0 SCRAMNet Write Posting off 10.9/15.0 10.9/15.0 I/O PERFORMANCE in V3 from V3 from...
Page 75 SPECIFICATIONS A.4 Board Dimensions Figure A-1 PMC Dimensions Copyright 2003 SC 150 SC150 PMC H/W REFERENCE...
Page 76 SPECIFICATIONS A.5 PMC Bus Voltage Specification Mnemonic Description Allowed Ripple/Noise Variation Below 10 MHz +5 V +5 V dc +0.25 V/-0.125 V 50 Mv +12 V +12 dc power +0.60 V/-0.36 V 50 Mv -12 V -12 dc power -0.60 V/+0.36 V 50 Mv +5 V STDBY +5 V dc standby...
Page 77 SPECIFICATIONS A.6 Fiber Optic Bypass Switch Figure A-2 Fiber Optic Bypass Switch Copyright 2003 SC 150 SC150 PMC H/W REFERENCE...
Page 78 SPECIFICATIONS Figure A-3 Housing Dimensions Copyright 2003 SC 150 SC150 PMC H/W REFERENCE...
Page 79 APPENDIX B CSR DESCRIPTIONS TABLE OF CONTENTS B.1 Description ............................B-1 B.1.1 CSR0—General SCRAMNet+ SC150 Enable and Reset (READ/WRITE) ...... B-2 B.1.2 CSR1—Error Indicators ....................B-4 B.1.3 CSR2—Node Control (READ/WRITE) ................B-6 B.1.4 CSR3—Node Information (READ ONLY)..............B-8 B.1.5 CSR4—Interrupt Address (LSP) (READ ONLY)............B-8 B.1.6 CSR5—Interrupt Address and Status (READ ONLY)* ...........
Page 81 CSR DESCRIPTIONS B.1 Description This section describes each Control/Status Register and the function of each bit. The name of each bit is indicative of its set state. The registers are described using bit 0 as the Least Significant Bit (LSB). For example: Inserting 0xA7C3 in a 16-bit register would set bits 0, 1, 6, 7, 8, 9, 10, 13, and 15 ON.
Page 82 Auxiliary Control RAM Enable - When this bit is set, the ACR bytes are swapped in place of the corresponding least-significant byte of every four-byte word in SCRAMNet+ SC150 memory. The values written to those ACR byte locations dictate the type of interrupt to occur when the 4-byte memory location is written into.
Page 83 When set, the data-filter function is enabled for the address space above the first 4 K bytes of SCRAMNet+ SC150 memory. Bit 11 controls the lower 4 K bytes. Enable Lower 4 K Bytes For Data Filter - When set, the lower 4 K bytes of address space is data filtered if bit 10 is also set.
Page 84 This occurs when there is more data coming from the host to the network than the network can absorb. When the shared memory is full, host writes are held off by the SCRAMNet+ SC150 host interface logic until the Transmit FIFO is no longer full.
Page 85 CSR DESCRIPTIONS Bits Description Interrupts Armed - During interrupt operation, this bit indicates that the conditions to receive an interrupt are active. If this bit is ‘0’, then the host receives no interrupts. When CSR1 is written to, then the interrupts-armed bit returns to an active status. Fiber Optic Bypass Not Connected - This is a status bit concerning the installation of the optional Fiber Optic Bypass Switch.
Page 86 CSR DESCRIPTIONS B.1.3 CSR2—Node Control (READ/WRITE) Table B-3 CSR2 Bits Description These bits are related to lines connected through the MUX control port and are available to the host interface. They are not required to connect to anything Disable Fiber Optic Loopback - When this bit is ‘0’ (power up default), the output of the transmitter is connected by fiber optics directly to the input of the receiver, and the receiver is disconnected from the network.
Page 87 No Network Error Correction - This bit is used in conjunction with CSR2[12] and CSR2[14] to enable communication protocols: BURST or PLATINUM mode and the variable length message PLUS ( ) mode (see below). SCRAMNet+ SC150 Protocol Mode Definition CSR2[15] CSR2[14] CSR2[12]...
Page 88 Bits Description Node Number Count - These bits represent the total number of SCRAMNet+ SC150 nodes on the network. This value is dynamically determined by the hardware and ranges from 0 to 255 depending upon the number of nodes actually on the network.
Page 89 Table B-8 CSR7 Bits Description 15-0 Not Used B.1.9 CSR8—General SCRAMNet+ SC150 Extended Control Register Table B-9 CSR8 Bits Description ID Multiplex - When set, CSR3 contains the T_AGE and RXID fields. Disable Holdoff - When set, this bit disables the HOLDOFF feature.
Page 90 CSR DESCRIPTIONS B.1.10 CSR9—SCRAMNet+ SC150 Interrupt On-Error Mask* Table B-10 CSR9 Bits Description Transmit FIFO Full Mask Transmit FIFO not Empty Mask Transmit FIFO 7/8 Full Mask Built In Self Test Stream (BIST) - Internal 82-bit BIST shift register output.
Page 91 CSR DESCRIPTIONS B.1.12 CSR11—Reserved Bits Description 15-0 Not Used B.1.13 CSR12—SCRAMNet+ SC150 Virtual Paging Register Table B-12 CSR12 Bits Virtual Paging Enable. When ON, this bit enables Virtual Paging. Always zero VP_A12 VP_A13 VP_A14 VP_A15 VP_A16 Virtual Page number. The significance of this register is dependent on the VP_A17 memory size.
Page 92 CSR DESCRIPTIONS B.1.14 CSR13—General Purpose Counter/Timer Table B-13 CSR13 Bits Description RD_COUNT[0] RD_COUNT[1] RD_COUNT[2] RD_COUNT[3] RD_COUNT[4] RD_COUNT[5] RD_COUNT[6] This is a General Purpose Counter/Timer register. It can be used to RD_COUNT[7] count trigger 1 and 2 events, count errors, or other events as RD_COUNT[8] programmed by CSR9[13] and CSR9[14].
Page 93 C C - CSR SUMMARY APPENDIX C CSR SUMMARY TABLE OF CONTENTS C.1 CSR0 - General SCRAMNet+ SC150 Enable and Reset ..............C-1 C.2 CSR1 - Error Indicators ........................C-2 C.3 CSR2 - Node Control ........................C-3 C.4 CSR3 - Node Information ......................... C-4 C.5 CSR4 - Interrupt Address (LSW)......................
Page 95 CSR SUMMARY C.1 CSR0 - General SCRAMNet+ SC150 Enable and Reset Function Name Receive Enable RX_ENB Transmit Enable TXEN Redundant TxRx Toggle Host Interrupt Enable Auxiliary Control RAM Enable ACRE Interrupt on Memory Mask Match Enable IMME Override RIE Flag...
Page 96 CSR SUMMARY C.2 CSR1 - Error Indicators Function Name Transmit FIFO Full TXFF Transmit FIFO Not Empty TXFNE Transmit FIFO 7/8 Full TXFAF (Always 0) Not Used Interrupt FIFO Full Protocol Violation Carrier Detect Failure Bad Message Receiver Overflow Transmit Retry TXRTY Transmit Retry Time-out Redundant TxRx Fault...
Page 97 No Network Error Correction NO_ERR_CRCT Write-Me-Last/Self-Interrupt Mode Definition Bit 10 Bit 9 Bit 8 Mode WRITE ME LAST mode SELF-INTERRUPT mode WRITE ME LAST with SELF-INTERRUPT mode SCRAMNet+ SC150 Protocol Mode Definition CSR2[15] CSR2[14] CSR2[12] CSR2[11] Network No Error Multiple Variable Message Size...
Page 98 CSR SUMMARY C.4 CSR3 - Node Information Function Name Node Number Count* (Valid After a Transmission from the Node) NID0 NID1 NID2 Node ID Number* NID3 NID4 NID5 NID6 NID7 When ID_MUX CSR8[0] is set: Bits 0 - 7 are Transmit AGE Bits 8 - 15 are Receive ID.
Page 99 CSR SUMMARY C.5 CSR4 - Interrupt Address (LSW) Function Name Always = 0 Always = 0 RFA2 RFA3 RFA4 RFA5 Interrupt FIFO Address Field (LSW) RFA6 RFA7 RFA8 RFA9 RFA10 RFA11 RFA12 RFA13 RFA14 RFA15 Copyright 2003 SC150 PMC H/W REFERENCE...
Page 100 ‘0’. A value of ‘0’ prevents host-generated data from leaving the Transmit FIFO C.7 CSR6 - Reserved A 16-bit, read only Systran reserved register. C.8 CSR7 - Reserved A 16-bit, read only Systran reserved register. Copyright 2003...
Page 101 CSR SUMMARY C.9 CSR8 - General SCRAMNet+ SC150 Extended Control Register Function Name 1 is CSR3=T_AGE & RXID fields ID_MUX Disable HOLDOFF feature DIS_HOLD Chip select to EEPROM CSR_CS0 Ext. Chip Select for AUX MICROWIRE CSR_CS1 peripheral MICROWIRE DOUT pin...
Page 102 CSR SUMMARY C.10 CSR9 - SCRAMNet+ SC150 Interrupt-On-Error Mask Function Name Transmit FIFO Full mask M_TX_F_F Transmit FIFO Not Empty mask M_TX_F_E Transmit FIFO 7/8 Full Mask M_TX_F_AF Internal 82 bit BIST shift register output BIST_STREAM Receiver FIFO Full Mask...
Page 103 CSR SUMMARY C.11 CSR10 - Write Posting Control Function Name 1 = Write Posting enabled 0 = Write Posting disabled 15-1 Not Used SMA15 C.12 CSR11 - Reserved A 16-bit, read only Systran reserved register. Copyright 2003 SC150 PMC H/W REFERENCE...
Page 104 CSR SUMMARY C.13 CSR12 - SCRAMNet+ SC150 Virtual Paging Register (Refer to Chapter 5, section 5.2.1, and Appendix B, page B-11 for additional information) Function Name Enables Virtual Paging when set Always ‘0’ VP_A12 VP_A13 VP_A14 VP_A15 Virtual Page Number...
Page 105 CSR SUMMARY C.14 CSR13 - SCRAMNet+ SC150 General Purpose Counter Timer (Refer to Chapter 5, section 5.10, and Appendix B, page B-12 for additional information) Function Name Counter/Timer register RD_COUNT[0] Counter/Timer register RD_COUNT[1] Counter/Timer register RD_COUNT[2] Counter/Timer register RD_COUNT[3] Counter/Timer register...
Page 106 CSR SUMMARY This page intentionally left blank Copyright 2003 C-12 SC150 PMC H/W REFERENCE...
Page 107 D D - CONFIGURATION AIDS APPENDIX D CONFIGURATION AIDS...
Page 109 CONFIGURATION AIDS SCRAMNet+ SC150 CONTROL/STATUS REGISTERS REFERENCE SHEET CSR 0 CSR 2 CSR 4 CSR 6 always 0 RX ENB available to host reserved always 0 TX ENB available to host reserved REDUND LINK TOGGLE available to host reserved RFA 2...
Page 110 CONFIGURATION AIDS * Write to CSR1 to re-arm interrupts. CSR 8 CSR 10 CSR 12 CSR 14 AGE & RXID MUX WRITE POST ENB VIRT PG ENB reserved HOLDOFF DISABLE reserved always 0 reserved CHP SELECT EEPROM reserved always 0 reserved AUX MICROWIRE reserved...
Page 111 SCRAMNet+ SC150 NETWORK CONFIGURATION DATA SHEET MEMORY NODE HOST MEMORY SCRAMNet ADDRESS ADDRESS MACHINE SIZE LEVEL SERIAL # & BUS & BUS...
Page 113 E E - PASSIVE PMC CABINET KIT APPENDIX E PASSIVE PMC CABINET KIT TABLE OF CONTENTS 1.1 Overview............................E-1 1.2 Description ............................E-1 1.3 Media Card............................E-1 1.4 Installation............................E-1 FIGURES Figure E-1 Bulkhead Plate Connections ....................E-1 Figure E-2 Passive PMC Cabinet Kit ...................... E-2...
Page 115 PASSIVE PMC CABINET KIT E.1 Overview This section discusses the Passive PMC Cabinet Kit used with the SCRAMNet+ SC150 Network PMC card in an enclosed chassis. This includes the cabinet kit features, functions, installation, and operation. E.2 Description The Passive PMC Cabinet Kit for the SCRAMNet+ SC150 Network provides fiber-optic access to the node’s connections, and maintains the shielding of the chassis.
Page 116 PASSIVE PMC CABINET KIT Figure E-2 Passive PMC Cabinet Kit Copyright 2003 SC150 PMC H/W REFERENCE...
Page 117 F F - ½ LENGTH PCI APPENDIX F ½ LENGTH PCI...
Page 119 The product consists of a PMC board mounted on a short-length PCI adapter board. This product has all the functionality of the SCRAMNet+ SC150 PMC board except that it is designed to be installed in a standard PCI slot. Only one SCRAMNet+ SC150 ½-Length...
Page 120 ½ LENGTH PCI ADAPTER This page intentionally left blank Copyright 2003 SC150 PMC H/W REFERENCE...
Page 121 1. GLOSSARY GLOSSARY...
Page 123 GLOSSARY A16 ----------------------------------A type of module that provides or decodes an address on address lines A01 through A15. A24 ----------------------------------A type of module that provides or decodes an address on address lines A01 through A23. A32 ----------------------------------A type of module that provides or decodes and address on address lines A01 through A31.
Page 124 GLOSSARY data filter---------------------------A process of comparing a host write to shared memory with contents of the specified memory location to eliminate transmission of redundant data and reduce network traffic. deterministic ----------------------Completely predictable message transit time from application to application. data transfer bus -----------------One of the four buses provided by the backplane. The data transfer bus allows masters to direct the transfer of binary data between themselves and slaves (data transfer bus is often abbreviated DTB).
Page 125 GLOSSARY latched ------------------------------Data is electrically stored in a circuit until it is needed. A method of coordinating two synchronous events. locking a page in memory ------Making a page ineligible for either paging or swapping. A page stays locked in physical memory until the operating system specifically unlocks it.
Page 126 GLOSSARY read-modify-write cycle --------A DTB cycle that is used to both read from, and write to, a slave's byte location(s) without permitting any other master to access that location during that cycle. This cycle is most useful in multi-processing systems where certain memory locations are used to control access to certain systems resources, for example, semaphore locations.
Page 127 GLOSSARY time-out-----------------------------Also network time-out. The time written to CSR5 that must elapse before a native message will be retransmitted. The time-out must be a non-zero value. Tx ------------------------------------Abbreviation for transmit or transmitter. UAT ---------------------------------A master that sends or receives data in an unaligned fashion. utility bus --------------------------One of the four buses provided by the backplane.
Page 128 GLOSSARY This page intentionally left blank Copyright 2003 GLOSSARY-6 SC150 PMC H/W REFERENCE...
Page 129 1. INDEX INDEX...
Page 131 INDEX RS-422/485 ............. 3-5 connector fibre-optic.......... 4-3, 4-4, 4-5 ACR ....1-1, 2-5, 4-8, 5-10, 5-15, 5-16, 5-19, media card............4-6 enable ..........5-8, B-2, C-1 ST ..............4-5 external triggers ..... 2-6, 5-8, 5-12, 5-15, 5-16 corrupted packets ..........2-4 external trigger 1.......
Page 132 INDEX write enable ............ C-3 holdoff mode ........B-9, C-7, D-2 feature disable............B-9 dual memory............3-2 host interrupt dual-port memory..........3-2 enable............B-2, C-1 dynamic shared memory........3-2 host to memory write error interrupt...........3-2 disable.............B-6, C-3 error interrupt mask..........3-2 humidity range............ A-1 general purpose counter/timer......3-2 variable-length message ........3-2 virtual paging...........3-2 insert mode ....5-19, 5-24, 5-25, B-3, B-6, C-1...
Page 133 INDEX memory network interrupt data .......... 2-8 address..2-1, 4-10, 5-2, 5-3, 5-5, 5-8, 5-15, 5-19 received............2-6 common blocks ..........5-3 network interrupt writes ........2-6 general purpose ..........2-1 forced ..........2-6, 2-8, 5-10 map............2-3, 5-1 selected ..........2-6, 5-10 pages ...............5-3 network interrupts size ..............4-11...
Page 134 INDEX receiving node..........2-5, 2-9 global .............. 2-8 redundant transceiver......B-2, B-4, B-20 transaction fault ..............B-4 network write ........2-1, 2-9, 5-17 mask............C-8 transmission rate ..........A-1 register transmit retry ............5-6 control/status......2-3, 3-4, 4-1, 4-7, time-out............5-6 4-8, 4-9, 5-3, 5-8, B-1 transmit general purpose counter/timer......

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