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PIN
5-V
NO.
NAME
I/O
TOLERANT
24 MDI/SDA
I/O
Yes
Software control I/F, SPI data input / I2C data input/output(2)
(3)
25 MC/SCL
I
Yes
Software control I/F, SPI clock input / I2C clock input(2)
26 MS/ADR1
I
Yes
Software control I/F, SPI chip select / I2C slave address
setting1(2)
27 MODE
I
No
Control mode setting, (see the Serial Control Mode section,
Control Mode Pin Setting)
28 RXIN7/ADIN0
I
Yes
Biphase signal, input 7 / AUXIN0, serial audio data input(2)
29 RXIN6/ALRCKI0
I
Yes
Biphase signal, input 6 / AUXIN0, LR clock input(2)
30 RXIN5/ABCKI0
I
Yes
Biphase signal, input 5 / AUXIN0, bit clock input(2)
31 RXIN4/ASCKI0
I
Yes
Biphase signal, input 4 / AUXIN0, system clock input(2)
32 RXIN3
I
Yes
Biphase signal, input 3(2)
33 RXIN2
I
Yes
Biphase signal, input 2(2)
34 RST
I
Yes
Reset Input, active low(2) (4)
35 RXIN1
I
Yes
Biphase signal, input 1, built-in coaxial amplifier
36 VDDRX
–
–
Power supply, 3.3 V (typ.), for RXIN0 and RXIN1.
37 RXIN0
I
Yes
Biphase signal, input 0, built-in coaxial amplifier
38 GNDRX
-
-
Ground, for RXIN
39 XTI
I
No
Oscillation circuit input for crystal resonator or external XTI
clock source input(5)
40 XTO
O
No
Oscillation circuit output for crystal resonator
41 AGND
–
–
Ground, for PLL analog
42 VCC
–
–
Power supply, 3.3 V (typ.), for PLL analog
43 FILT
O
No
External PLL loop filter connection terminal; must connect
recommended filter
44 VCOM
O
No
ADC common voltage output; must connect external
decoupling capacitor
45 AGNDAD
–
–
Ground, for ADC analog
46 VCCAD
–
–
Power supply, 5.0 V (typ.), for ADC analog
47 VINL
I
No
ADC analog voltage input, left channel
48 VINR
I
No
ADC analog voltage input, right channel
(1) Schmitt trigger input
(2) Schmitt trigger input
(3) Open-drain configuration in I2C mode
(4) Onboard pull-down resistor (50 k Ω , typical)
(5) CMOS Schmitt trigger input
PCM9211 BLOCK DIAGRAM
DESCRIPTION
65
www.ti.com
BLOCK DIAGRAM
FILT
AUXIN 0
AUTO
DIR
RXIN 0
RXIN0
DIR
RXIN 1
RXIN1
ADC
PLL
RXIN 2
RXIN2
AUXIN0
AUXIN1
RXIN 3
RXIN3
Lock :DIR
AUXIN2
RXIN 4/ASCKI 0
RXIN4
Unlock:ADC
RXIN 5/ABCKI 0
RXIN5
Clock/ Data
Recovery
RXIN 6/ALRCKI 0
RXIN6
RXIN 7/ADIN0
RXIN7
AUTO
DIR
MPIO_ A0
RXIN8
ADC
Lock Detection
MPIO_ A1
RXIN9
AUXIN0
MPIO_ A
MPIO_ A2
RXIN10
AUXIN1
SELECTOR
MPIO_ A3
RXIN11
RECOUT 0
AUXIN2
DITOUT
RECOUT 1
ADC
VINL
ADC Mode
ADC
VINR
Control
VCOM
Com. Supply
AUTO
MPIO _C0
DIR
ADC Standalone
MPIO _C1
ADC
MPIO_ C
MPIO _C2
AUXIN0
SELECTOR
AUXIN1
MPIO _C3
AUXIN1
ADC Clock
(SCK /BCK/LRCK)
XTI
Divider
XTO
OSC
XMCKO
(To MPIO _A & MPO0/1 )
XMCKO
Divider
REGISTER
MC /SCL
DIR
DIR
MDI /SDA
Function
DIR CS
2
SPI/I C
Control
( 48-bit)
P and P
f Calculator
C
D
S
MDO /ADR 0
INTERFACE
MS/ADR 1
GPIO/GPO
DIT CS
All Port
DIR Interrupt
f Calculator
Data
( 48-bit)
S
POWER SUPPLY
RST
Reset
and Mode
ADC
DIR
DIR
MODE
ALL
Set
ANALOG
ANALOG
ANALOG
VCCAD
AGNDAD
VCC
AGND
VDDRX
GNDRX
DVDD
DGND
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s):
PCM9211
PCM9211
SBAS495 – JUNE 2010
RXIN7
SCKO
DOUT
BCK
MAIN
OUTPUT
LRCK
SCKO/ BCK/LRCK
PORT
DOUT
DIT
RECOUT0
MPO 0
RECOUT1
MPO0/1
MPO 1
SELECTOR
DITOUT
MPIO_B0
MPIO_B1
AUXOUT
MPIO _B
MPIO_B2
SELECTOR
AUXIN 2
MPIO_B3
SBCK /SLRCK
Secondary BCK / LRCK
( to MPIO_A )
Divider
Selector
EXTRA DIR FUNCTIONS
ERROR /INT0
ERROR DETECTION
NPCM /INT1
Non-PCM DETECTION
f Calculator
S
MPIO_ A
Flags
MPIO_ B
DTS-CD/LD Detection
Validity Flag
MPIO_ C
User Data
MPO0
Channel Status Data
MPO1
BFRAME Detection
Interrupt System
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