4.11
BW/CVF SCHEMATIC DIAGRAM
TO DSP
BWBLEVEL
5
TO REG
REG_3.2V
SCK3
TO CPU
R7338
∗
VF_CS
SO3
CN11
OPEN
∗
CVF_SO3
CVF_SCK3
4
CVF_CS
GND
TO REG
REG+12V
TO CPU
VF_CTL
TO REG
REG_4.8V
TO CPU
V_PLS_ON
For PANA MODEL
CN9025
∗
Q7308
GND
3
BWVFADJ
VDCVF
TO DSP
HDCVF
CN25
BWVFADJ
JIG_CONN.
GND
BWYGAIN
TO DSP
Y
BWYOUT
CN12
Y
2
BW_VF_Y
TO E. VF
GND
CN7002
VF_BL4.8
C7326
10
/6.3
R7330
∗
Q7310
CPH3101-X
R7332
1.5k
R7333
47k
C7325
1
10
/6.3
NOTE : The parts with marked ( ) is not used.
A
B
R7337
∗
IC7302
∗
NC
∗
D7301
NC
R7334
∗
VDDH
C7318
∗
TEST
L7302
R7335
∗
SEL_PDR
∗
∗
VBAT
C7321
∗
A_VBAT
H_SYNC
V_SYNC
VHIO_SEL
R7301
1.8k
R7302
∗
R7309
∗
Q7301
2SA1774/QR/-X
R7327
∗
Q7306
∗
Q7307
∗
T
Q7311
2SC4617/QR/-X
∗
C
NOTES :
For the destination of each signal and further line connections that are cut off from
this diagram , refer to "4.1 BOARD INTERCONNECTIONS".
When ordering parts , be sure to order according to the Part Number indicated in the Parts List.
Q7303
∗
C7312
∗
HPL
V_REF
VSS
IC7301
VDD
∗
VEE
V_COM
HODL
VPL
VCK
VIDH
R7313
R7306
∗
GAIN
D
E
4-23
4-24
Q7305
∗
Q7304
∗
C7311
∗
C7310
∗
C7309
∗
C7308
∗
∗
0 1 MAIN (BW/CVF)
M2_MAIN_BW/CVF_BLOCK
JVC_BWVF_MODEL
F
OPEN
CN11
∗
VF_BLK
REG_4.8V
CN9012
∗
For PANA MODEL
GND
BWVFADJ
RENON
RENEN
HCLKN
HPLN
VF_BLK
VREF
GND
BW_VDD
REG_4.8V
BW_VEE
BW_COM
HLTOR
HODL
VPLN
VCKN
VIDHI
PDR
GND
y30155001a_rev0
G
H