Related Manuals for Design Gateway IP Lock
Summary of Contents for Design Gateway IP Lock
- Page 1 IP Lock (standard pack) User s Manual Design Gateway Co.,Ltd. Rev 1.5 (PD0602-6-01-05E) *** Please read this manual carefully before using IP Lock (standard pack)***...
- Page 3 Detail of change 10 May 2006 Initial Release 18 July 2006 Adding IP lock core for Altera FPGA. 19 October 2006 Update detail of setting internal pull-up on ISE Update detail of SC0 signal 8 November 2007 Support Xilinx Virtex5...
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Page 4: Table Of Contents
1.4. Customer Support ........................2 2. IP Lock System ..........................3 3. IP Lock core ............................4 3.1. IP Lock core for Xilinx FPGA ....................4 3.2. IP Lock core for Altera FPGA ....................4 4. IP Lock Device..........................6 5. Example VHDL design........................9 6. Troubleshooting ..........................10... -
Page 5: Introduction
1. Introduction Thank you very much for purchasing IP Lock. Please check that all the following items are in the box. If anything is missing or damaged, contact your distributor or Design Gateway Co.,Ltd. 1. IP Lock device 10 or 50 pcs. -
Page 6: Warranty Policy
Design Gateway Co.,Ltd). 1.4. Customer Support Customer can contact to support@design-gateway.com for support of any problem about IP Lock or visit our website at www.design-gateway.com. Your Personal information will be restricted with high confidentiality. -
Page 7: Ip Lock System
IP Lock core to enable user s logic. For IP Lock (standard pack) Design Gateway Co.,Ltd fix user s key in IP Lock core and IP Lock device so user can not change user s key value. And each IP Lock (standard pack) user s key value is not same value so user can not use IP Lock core and IP Lock device from different standard pack. -
Page 8: Ip Lock Core
- Xilinx IP Lock core (iplock.ngc and iplockex.ngo): IP Lock core communicate with IP Lock device for check user s key before enable ENABLE signal. If communication between IP Lock core and IP Lock device failed or user s key is not same value, IP Lock will disable ENABLE signal. - Page 9 - User s key value already fix in IP Lock core. - User must add IP Lock license into Quartus II license as shown in Figure 3-3 before start synthesis and implement HDL code. If user does not have IP Lock license, User can not synthesis and implement IP Lock core.
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Page 10: Ip Lock Device
FPGA (IP Lock core) all time. Figure 4-1 shows recommend schematic of IP Lock device. Voltage I/O of FPGA that connects to IP Lock device should be connecting to +3.3 - +5 V. Figure 4-1 Schematic of IP Lock Device... - Page 11 Figure 4-4 Setting internal pull up on Quartus II set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DC0 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DD0 Figure 4-5 Setting internal pull up on qsf file IP Lock (standard pack) User s Manual - 7 - PD0602-6-01-05E...
- Page 12 Figure 4-6 Package dimensions of IP Lock device Figure 4-7 Footprint of IP Lock device (All dimensions in inch) Figure 4-6 shows package dimensions of IP Lock device. Figure 4-7 shows footprint dimensions of IP Lock device. Figure 4-8 shows typical circuit of IP Lock device.
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Page 13: Example Vhdl Design
The example source codes compose of Counter.vhd and Counter32bits.vhd. Counter.vhd is example code that shows how to connect between user s logic and Top IP Lock. Counter32Bits.vhd is example code that shows how to use ENABLE signal in user s logic. The block diagram of example VHDL design as shown in Figure 5-1 Top Level of user s logic (Counter.vhd) -
Page 14: Troubleshooting
Q: Do you use IP Lock core and IP Lock device from same package? A: Because user s ID in IP Lock core and user s ID IP Lock device are same and fix, so if user use IP Lock core and IP Lock device from different package, IP Lock does not enable (disable). - Page 16 54 BB Building, 12 Floor, Room No.1201, Sukhumvit 21 Rd. (Asoke) Klongtoey-Nua, Wattana, Bangkok 10110 Thailand Tel. (662)261-2277, Fax. (662)261-2290 www.design-gateway.com...
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